ADDRESS GENERATION Execution of instructions by the CPU involves generation of the addresses of instructions and operands. This section describes address generation as it applies to most instructions. In some
instructions, the operation performed
does not follow the general rules stated
in this section. All of these exceptions are explicitly identified in
the individual instruction descriptions. SEQUENTIAL INSTRUCTION-ADDRESS GENER­ ATION When an instruction is fetched from the
location designated by the current PSW, the instruction address is increased by
the number of bytes in the instruction,
and the instruction is executed. The same steps are then repeated by using
the new value of the instruction address
to fetch the next instruction in the
sequence.
Instruction addresses wrap around, with
the halfword at instruction address 224 - 2 being followed by the halfword
at instruction address o. Thus, any
carry out of PSW bit position 40, as a result of updating the instruction
address, is lost. OPERAND-ADDRESS GENERATION An operand address that refers to stor­ age either is contained in a register designated by an R field in the instruc­
tion or is calculated from the sum of three binary numbers: base address, index, and displacement.
The base address (n) is a 24-bit number
contained in a general register speci­ fied by the program in a four-bit field,
called the B field, in the instruction.
Base addresses can be used as a means of
independently addressing each program
and data area. In array-type calcu­
lations, it can designate the location
of an array, and, in record-type proc­
essing, it can identify the record. The
base address provides for addressing the
entire storage. The base address may
also be used for indexing.
The index (X) is a 24-bit number
contained in a general register desig­ nated by the program in a four-bit field, called the X field, in the
instruction. It is included only in the
address specified by the RX-format
instructions. The RX-format instruc-
tions permit double indexing; that is,
the index can be used to provide the
address of an element within an array.
The displacement (D) is a 12-bit number contained in a field, called the D
field, in the instruction. The
displacement provides for relative
addressing of up to 4,095 bytes beyond
the location designated by the base
address. In array-type calculations,
the displacement can be used to specify one of many items associated with an
element. In the processing of records, the displacement can be used to identify
items within a record.
In forming the address, the base address
and index are treated as 24-bit binary integers. The displacement is similarly
treated as a 12-bit unsigned binary integer, and 12 zeros are appended on
the left. The three are added as 24-bit
binary numbers, ignoring overflow. The
sum is always 24 bits long. The bits of
the generated address are numbered 8-31,
corresponding to the numbering of the
base-address and index bits in the
general register.
A zero in any of the Bt, B21 or X 2 fields indicates the absence of the
corresponding address component. For
the absent component, a zero is used in
forming the address, regardless of the
contents of general register O. A
displacement of zero has no special
significance.
When an instruction description speci­ fies that the contents of a general
register designated by an R field are
used to address an operand in storage,
bit positions 8-31 of the register
provide the operand address. For the
instructions INSERT STORAGE KEY
EXTENDED, RESET REFERENCE BIT EXTENDED,
SET STORAGE KEY EXTENDED, and TEST BLOCK, bits 1-31 of the register provide the address.
An instruction can designate the same
general register both for address compu­ tation and as the location of an
operand. Address computation is completed before registers, if any, are changed by the operation. Unless otherwise indicated in an indi­
vidual instruction definition, the
generated operand address designates the
leftmost byte of an operand in storage. Programming Note Negative values may be used in index and
base-address registers. Bits 0-7 of these values are always ignored.
Chapter 5. Program Execution 5-5

BRANCH-ADDRESS GENERATION For branch instructions, the address of
the next instruction to be executed when the branch is taken is called the branch
address. Depending on the branch
instruction, the instruction format may
be RR, RS, or RX.
In the RS and RX formats, the branch
address is specified by a base address, a displacement, and, for RX, an index.
In the RS and RX formats, the branch
address generation follows the normal
rules for operand-address generation.
In the RR format, the contents of bit
positions 8-31 of the general register designated by the R2 field are used as
the branch address, and bits 0-7 of the
register are ignored. General register
o cannot be designated as containing a
branch address. A value of zero in the R2 field causes the instruction to be executed without branching.
For several branch instructions, branch­
ing depends on satisfying a specified
condition. When the condition is not
satisfied, the branch is not taken,
normal sequential instruction execution
continues, and the branch address is not
used. When a branch is taken, bits 8-31
of the branch address replace bits 40-63 of the current PSW. The branch address
is not used to access storage as part of
the branch operation.
A specification exception due to an odd
branch address and access exceptions due
to fetching of the instruction at the
branch location are not recognized as
part of the branch operation but instead
are recognized as exceptions associated
with the execution of the instruction at the branch location.
A branch instruction, such as BRANCH AND LINK, can designate the same g~neral register for branch-address computation
and as the location of an operand.
Branch-address computation is completed
before the remainder of the operation is executed. INSTRUCTION EXECUTION AND SEQUENCING The program-status word (PSW), described
in Chapter 4, "Control," contains infor­
mation required for proper program
execution. The PSW is used to control
instruction sequencing and to hold and
indicate the status of the CPU in
relation to the program currently being
executed. The active or controlling PSW is called the current PSW. Branch instructions perform the func­
tions of decision making, loop control,
and subroutine linkage. A branch
5-6 System/370 Principles of Operation instruction affects instruction sequenc­
ing by introducing a new instruction
address into the current PSW. DECISION MAKING
Facilities for decision making are
provided by BRANCH ON CONDITION. This
instruction inspects a condition code
that reflects the result of a majority
of the arithmetic, logical, and I/O operations. The condition code, which
consists of two bits, provides for four
possible condition-code settings: 0, 1,
2, and 3.
The specific meaning of any setting
depends on the operation that sets the
condition code. For example, the condi­
tion code reflects such conditions as
zero, nonzero, first operand high,
equal, overflow, and channel busy. Once set, the condition code remains
unchanged until modified by an instruc­ tion that causes a different condition
code to be set. See Appendix C, "Condition-Code Settings," for a summary
of the instructions which set the condi­
tion code. LOOP CONTROL Loop control can be performed by the use
of BRANCH ON CONDITION to test the
outcome of address arithmetic and count­
ing operations. For some particularly
frequent combinations of arithmetic and
tests, BRANCH ON COUNT, BRANCH ON INDEX
HIGH, and BRANCH ON INDEX LOW OR EQUAL are provided. These branches, being
specialized, provide increased perform­
ance for these tasks. SUBROUTINE LINKAGE
Subroutine linkage is provided by the BRANCH AND LINK and BRANCH AND SAVE
instructions, which permit not only the
introduction of a new instruction
address but also the preservation of the
return address and associated informa­
tion. Linkage between a problem-state
program and the supervisor or monitoring
program is provided by means of the SUPERVISOR CALL and MONITOR CALL instructions.
The instructions PROGRAM CALL and PROGRAM TRANSFER provide the facility
for linkage between programs of differ­
ent authority and in different address
spaces. PROGRAM CALL permits linkage to
a number of preassigned programs that
may be in either the problem or the
supervisor state and may be in either