Explanation:  ¢   Causes   serialization  and  checkpoint  synchronization.  
¢lCauses   serialization  and  checkpoint  synchronization  when  the  Mt  and  R:z   fields  contain  all  ones  and  all  zeros,  respectively.  
$Causes   serialization.  
A Access exceptions for logical addresses.
AI Access exceptions for instruction address.
B PER branch event.BS   Branch-and-save  facility.  C   Condition   code  is   set.  
D Data exception.
EX Execute exception.
GM Instruction execution includes the implied use of general registers 1
and 2.
IF Fixed-point-overflow exception.
II Interruptible instruction.
IK Fixed-point-divide exception.
LHew   condition  code  is  loaded.  
MI Move-inverse facility.MO   Monitor  event.  
R PER general-register-alteration event.
RR RR instruction format.RS   RS   instruction  format.  
RX RX instruction format.S   S   instruction  format.  SI   SI   instruction  format.  SP   Specification   exception.  SS   SS   instruction  format.  
5T PER storage-alteration event.5W   Conditional-swapping  facility.  Summary   of  General  Instructions  (Part  3  of  3)  
ADD
AR R11   R2  [RR]  ,   1  A'  I   R  t  I   R2   I   0   8  12  15  
A Rt,D:z(X  
2
,B
2
) [RX]  
'SA'I   R  t  I   X:z   I   B2   D:z   0   8  12  16  20   31  
The second operand is added to the first
operand, and the sum is placed at the
first-operand location. The operands
and the sum are treatedas   32-bit  signed  
binary integers.
When there isan   overflow,  the  result  is  
obtained by allowing any carry into the
sign-bit position and ignoring any carry
out of the sign-bit position, and condi
tion code 3 is set. If the fixed
point-overflow mask is one, a program
interruption for fixed-point overflow
occurs.
ResultingCondition   Code:   o  Result  zero;   no  overflow  
1
2
3
Result less thanzero;   no  over  
flow
Result greater than zero; no
overflowOverflow   Program  Exceptions:  
Access (fetch, operand 2 of A only)
Fixed-point overflow
ADDHALFWORD   AH  [RX]  
'4A'
o 8 12 1620   31  
The second operand is added to the first
operand, and the sum is placed at the
first-operand location. The second
operand is two bytes in length and;s
treated as a 16-bit signed binary inte
ger. The first operand and the sum are
treated as 32-bit signed binary
integers.
When there is an overflow, the result is
obtained by allowing any carry into the
sign-bit position and ignoring any carry
out of the sign-bit position, and condi
tion code 3 is set. If the fixed-Chapter   7.  General  Instructions  7-7  
¢l
$
A Access exceptions for logical addresses.
AI Access exceptions for instruction address.
B PER branch event.
D Data exception.
EX Execute exception.
GM Instruction execution includes the implied use of general registers 1
and 2.
IF Fixed-point-overflow exception.
II Interruptible instruction.
IK Fixed-point-divide exception.
L
MI Move-inverse facility.
R PER general-register-alteration event.
RR RR instruction format.
RX RX instruction format.
5T PER storage-alteration event.
ADD
AR R
A Rt
2
,B
2
)
'SA'
The second operand is added to the first
operand, and the sum is placed at the
first-operand location. The operands
and the sum are treated
binary integers.
When there is
obtained by allowing any carry into the
sign-bit position and ignoring any carry
out of the sign-bit position, and condi
tion code 3 is set. If the fixed
point-overflow mask is one, a program
interruption for fixed-point overflow
occurs.
Resulting
1
2
3
Result less than
flow
Result greater than zero; no
overflow
Access (fetch, operand 2 of A only)
Fixed-point overflow
ADD
'4A'
o 8 12 16
The second operand is added to the first
operand, and the sum is placed at the
first-operand location. The second
operand is two bytes in length and;s
treated as a 16-bit signed binary inte
ger. The first operand and the sum are
treated as 32-bit signed binary
integers.
When there is an overflow, the result is
obtained by allowing any carry into the
sign-bit position and ignoring any carry
out of the sign-bit position, and condi
tion code 3 is set. If the fixed-
 
             
            












































































































































































































































































































































































































































































































































































