INTERVAL-TIMER CONTROL The interval-timer control disables or
enables operation of the interval timer.
Disabling the interval timer does not
affect any other facility.
When the control is set to the disable
position, updating of real-storage
locations 80-83 ceases. The contents of
the interval timer remain at the last
value to which they were updated, unless
changed by a subsequent store operation.
Depending on the model, any already­
pending interval-timer-interruption con­
dition is unaffected, is cleared, or is
kept pending without regard to the state
of the external mask, PSW bit 7, and the
interval-timer mask, bit 24 of control
register O. When the control is set to the enable
position, updating of real-storage
locations 80-83 is resumed by using the
current contents. If an interval­
timer-interruption request existed and
was kept pending when the interval-timer
control was last set to the disable
position, that condition remains pending
until the CPU is enabled for the inter­
ruption.
The enable position is considered the
normal position. The test indicator may
or may not be turned on when the
interval-timer control is set to the
disable position. Programming Note
Disabling the interval timer allows
execution of a program which uses real­
storage locations 80-83 as ordinary
storage. A program which does not use
the interval timer will function
correctly with the interval timer disa­
bled, even when the interval timer
fails. LOAD INDICATOR The load indicator is on during initial
program loading, indicating that the CPU is in the load state. The indicator
goes on for a particular CPU when the
load-clear or load-normal key is acti­
vated for that CPU and the corresponding
operation is started. It goes off after
the new PSW is loaded successfully. For
details, see the section "Initial Program Loading" in Chapter 4, "Control." LOAD-CLEAR KEY Activating the load-clear key causes a
reset operation to be performed and
initial program loading to be started by
using the channel and I/O device desig­
nated by the load-unit-address controls. Clear reset is performed on the config­
uration. For details, see the sections
"Resets" and "Initial Program Loading"
in Chapter 4, "Control." The load-clear key is effective when the CPU is in the operating, stopped, load,
or check-stop state. LOAD-NORMAL KEY Activating the load-normal key causes a
reset operation to be performed and
initial program loading to be started by
using the channel and I/O device desig­
nated by the load-unit-address controls.
Initial CPU reset is performed on the CPU for which the load-normal key was
activated, CPU reset is propagated to
all other CPUs in the configuration, and
a subsystem reset is performed on the
remainder of the configuration. For
details, see the sections "Resets" and
"Initial Program Loading" in Chapter 4, "Control." The load-normal key is effective when
the CPU is in the operating, stopped,
load, or check-stop state. LOAD-UNIT-ADDRESS CONTROLS The load-unit-address controls specify
the I/O address of the channel and the
device used for initial program loading.
For details, see the section "Initial Program Loading" in Chapter 4, "Control." MANUAL INDICATOR The manual indicator is on when the CPU is in the stopped state. Some functions
and several manual controls are effec­
tive only when the CPU is in the stopped
state. POWER CONTROLS The power controls are used to turn the
power on and off.
The CPUs, storage, channels, operator
facilities, and I/O devices may all have Chapter 12. Operator Facilities 12-3

their power turned on and off by common
controls, or they may have separate
power controls. When a particular unit
has its power turned on, that unit is
reset. The sequence is performed so
that no instructions or I/O operations
are performed until explicitly
specified. The controls may also permit
power to be turned on in stages, but the
machine does not become operational
until power on is complete.
When the power is completelY turned on,
an IML operation is performed on models
which have an IML function. A power-on
reset is then in~tiated (see the ~ection "Resets" in Chapter 4, "Control"). RATE CONTROL The setting of the rate control deter­
mines the effect of the start function
and the manner in which instructions are
executed.
The rate control has at least two posi­
tions. The normal position is the proc­
ess position. Another position is the
instruction-step position. When the
rate control is set to the process posi­
tion and the start function is
performed, the CPU starts operating at
normal speed. When the rate control is
set to the instruction-step position and
the wait-state bit is zero, one instruc­
tion or, for interruptible instructions,
one unit of operation is executed, and
all pending allowed interruptions are
taken before the CPU returns to the
stopped state. When the rate control is
set to the instruction-step position and
the wait-state bit is one, no instruc­
tion is executed, but all pending
allowed interruptions are taken before
the CPU returns to the stopped state.
For details, see the section "Stopped, Operating, Load, and Check-Stop States"
in Chapter 4, "Control." The test indicator is on while the rate
control is not set to the process posi­
tion.
If the setting of the rate control is
changed while the CPU is in the operat-
1ng or load state, the results are
unpredictable.
RESTART KEY
Activating the restart key
restart interruption. (See
"Restart Interruption" in
"Interruptions.")
initiates a
the section Chapter 6,
12-4 System/370 Principles of Operation The restart key is effective when the CPU is in the operating or stopped
state. The key is not effective when
the CPU is in the check-stop state. It
depends on the model whether the restart
key is effective when any CPU in the
configuration is in the load state.
The effect is unpredictable when the
restart key is activated while any CPU in the configuration is in the load
state. In particular, if the CPU performs a restart interruption and
enters the operating state while another CPU is in the load state, operations
such as I/O instructions, the SIGNAL PROCESSOR instruction, and the INVALI­
DATE PAGE TABLE ENTRY instruction may
not operate according to the definitions
given in this publication.
START KEY
Activating the start key causes the CPU to perform the start function. (See the
section "Stopped, Operating, Load, and Check-Stop States" in Chapter 4, "Con­ trol.")
The start key is effective only when the CPU is in the stopped state. The effect is unpredictable when the stopped state
has been entered by a reset. STOP KEY
Activating the stop key causes the CPU to perform the stop function. (See the
section "Stopped, Operating, Load, and Check-Stop States" in Chapter 4, "Con­ trol.")
The stop key is effective only when the CPU is in the operating state. Operation Note Activating the stop key
when: • An unending string
program or external
occurs.
has no effect
of certain
interruptions • The prefix register contains an
invalid address. • • The CPU is in the load or check­
stop state.
A READ DIRECT instruction cannot be
completed.