1. The validity of the information
loaded into a control register,
including that pertaining to dynam­
ic address translation, is not
checked at the time the register is
loaded. This information is
checked and the program exception,
if any, is indicated at the time
the information is used.
2. The information pertaining to
dynamic address translation is
considered to be used when an
instruction is executed with OAT on
or when INVALIDATE PAGE TABLE ENTRY or lOAD REAL ADDRESS is executed.
The information is not considered
to be used when the PSW specifies
translation but an I/O, external,
restart, or machine-check inter­
ruption occurs before an instruc­
tion is executed, or when the PSW specifies the wait state. TRANSLATION TABLES The translation process consists in a
two-level lookup using two tables: a
segment table and a page table. These
tables reside in real storage.
Segment-Table Entries
The entry fetched from the segment table
has the following format: IPTl 10000 1 Page-Table Origin 048 29 31
The fields in the segment-table entry
are allocated as follows: Page-Table Length (PTl): Bits 0-3 spec­
ify the length of the page table in
increments that are equal to 1/16 of the
maximum size of the table, the maximum
size depending on the size of segments
and pages. The length of the page
table, in units 1/16 of the maXlmum
size, is one more than the PTl value.
The length field is compared against the
leftmost four bits of the page-index
portion of the virtual address to deter­
mine whether the page index designates
an entry within the page table. Page-Table Origin: Bits 8-28, with
three zeros appended on the right, form a 24-bit real address that designates
the beginning of a page table. With
extended real addressing, the page-table
origin is still a 24-bit real address
and is extended on the left with zeros. Segment-Protection Bit (f): Bit 29,
with the segment-protection facility
installed, controls whether store
accesses can be made in the segment.
This protection mechanism is in addition
to the key-controlled-protection and
low-address-protection mechanisms. The
bit has no effect on fetch accesses. If
the bit is zero, stores are permitted to
the segment, subject to the other
protection mechanisms. If the bit is
one, stores are disallowed. An attempt
to store when the segment-protection bit
is one causes a protection exception to
be recognized.
Common-Segment Bit (~): Bit 30, with
the common-segment facility installed,
controls the use of translation­
lookaside-buffer (TlB) copies of the
segment-table entry and of the page
table which it designates. A zero iden­
tifies a private segment; in this case,
the segment-table entry and the page
table it designates may be used only in
association with the segment-table
origin that designates the segment table
in which the segment-table entry
resides. A one identifies a common
segment; in this case, the segment-table
entry and the page table it designates
may continue to be used for translating
addresses corresponding to the segment
index, even though a different segment
table is specified. In some models, bit 30 in the segment-table entry is
ignored, and all segments are treated as
private.
The common-segment bit is used only for
controlling the loading and use of TLB
copies. When the common-segment facili­
ty is installed, the common-segment bit
is ignored for explicit translation and
for implicit translation not using the
TLB.
Segment-Invalid Bit (1): Bit 31
controls whether the segment associated
with the segment-table entry is avail­
able. When the bit is zero, address
translation proceeds by using the desig­
nated page table. When the bit is a one, the segment-table entry cannot be
used for translation.
The handling of bit positions 4-7 and 29-30 of the segment-table entry depends
on the model. Normally a translation­
specification exception is recognized
when these bits are not zeros; however,
on some models the contents of these bit
positions maybe ignored. On machines
with the segment-protection facility
installed, bit 29 is interpreted as the
segment-protection bit. On machines
with the common-segment facility
installed, bit 30 is interpreted as
defined or is ignored.
Chapter 3. Storage 3-25

Page-Table Entries
The format of the page-table entry
depends on page size, as follows:
Page-table entry with 4K-byte pages:
PFRA
o 12 15
Page-table entry with 2K-byte pages: PFRA o 13 15
The fields in the page-table entry are
allocated as follows: Page-Frame Real Address (PFRA): Bits 0-11 or bits 0-12, depending on the page
size, provide the leftmost 12 or 13 bits of a 24-bit real storage address. When
these bits are concatenated with the
contents of the byte-index field of the
virtual address on the right, a 24-bit
real storage address is obtained. Page-Invalid Bit (I): Bit 12 or 13, depending on the page size, controls
whether the page associated with the page-table entry is available. When the
bit is zero, address translation
proceeds by using the page-table entry.
When the bit is one, the page-table
entry cannot be used for translation.
Extended-storage-Address Bits (EA):
When the extended-real-addressing facil­
ity is installed, bits 13 and 14 of the
page-table entry with 4K-byte pages are
the extended-storage-address bits.
These bits become bits 6 and 7 of a 26-bit real address.
Except for bit position
positions to the right 15, the bit
of the page-
3-26 System/370 Principles of Operation invalid bit must contain zeros; other­ wise, a translation-specification
exception is recognized as part of the
execution of an instruction using that
entry for address translation. In
models that provide the extended-real­
addressing facility, bit positions 13
and 14 of the page-table entry for
4K-byte pages are used as the extended­
storage-address bits and do not cause a translation-specification exception.
Bit position 15 is unassigned and not
checked for zero. SUMMARY OF DYNAMIC-ADDRESS-TRANSLATION FORMATS The first table summarizes the possible
combinations of the page-frame real
address (PFRA) field, byte-index field, and extended-storage-address bits in the
formation of a real storage address.
The eight-bit length field in the segment-table designation provides for a maximum length code of 255 and permits
designating a segment table of 16,384
bytes, or 4,096 entries, which is more
than can be referred to for translation
purposes by the virtual address. With
1M-byte segments, only 16 segments can be selected, requiring a segment table
of 64 bytes. A table of 64 bytes is
specified by a length code of 0 and is
the smallest table that can be
specified. With 64K-byte segments, up
to 256 segments can be selected, requir­
ing at the most a segment table of 1,024 bytes and a length code of 15. These relations are summarized in the second table. The third table lists the maximum sizes of the page table and the increments in
which the size of the page table can be controlled.