Machine Format Op Code R
t
44 1 ° A 0001 Assembler Format
EX 1,0(0,10) where register 10 contains 00 00 38 20 and register 1 contains 00 OF FO 03. When the instruction at 5000 is
executed, the rightmost byte of register
1 is ORed with the second byte of the
target instruction:
Instruction byte:
Register byte: 0000 0000{2} = 00 0000 0011{2} = 03 Result: 0000 0011{2} = 03 causing the instruction at 3820 to
executed as if it originally were:
Machine Format Op Code L Bt Dt B2 O 2 02 03 C 003
1 0 0001 Assembler Format MVC 3(4,12),0(13) However, after execution:
Register 1 is unchanged.
be
The instruction at 3820 is unchanged.
The contents of the four bytes starting
at location 90AO have been moved to
the four bytes starting at location
8916.
The CPU next executes the instruction
at address 5004 (PSW bits 40-63 contain 00 50 04). INSERT CHARACTERS UNDER MASK (ICM) The INSERT CHARACTERS UNDER MASK (ICM) instruction may be used to replace all or selected bytes in a general register
with bytes from storage and to set the
condition code to indicate the value of
the inserted field.
For example, if it is desired to insert
a three-byte address from FIELDA into
register 5 and leave the leftmost byte
of the register unchanged, assume:
Machine Format Op Code BF 5 7 * * * * Assembler Format ICM 5,B'0111',FIELDA FIELDA:
Register 5 (before):
Register 5 (after): Condition code (after):
As another example:
Machine Format Op Code FE DC BA
12 34 56 78
12 FE DC BA
1 (leftmost
bit of
inserted
field is
one)
BF 6 9 * * * * Assembler Format ICM 6,B'1001',FIELDB FIELDB:
Register 6 (before):
Register 6 (after): Condition code (after):
12 34 00 00 00 00 12 00 00 34
2 (inserted
field is
nonzero
with left­
most zero
bit)
When the mask field contains 1111, the ICM instruction produces the same result
as LOAD (L) (provided that the indexing
capability of the RX format is not need­
ed), except that IeM also sets the
condition code. The condition-code
setting is useful when an all-zero field
(condition code 0) or a leftmost one bit
(condition code 1) is used as a flag.
Appendix A. Number Representation and Instruction-Use Examples A-19

LOAD (L, LR)
The LOAD instruction takes four bytes
from storage or from a general register
and place them unchanged into a general
register. For example, assume that the
four bytes starting with location 21003 are to be loaded into register 10. Initially:
Register 5 contains 00 02 00 00. Register 6 contains 00 00 10 03. The contents of register 10 are not
significant.
Storage locations 21003-21006 contain 00 00 AB CD. To load register 10, the RX form of the
instruction can be used:
Machine Format Op Code 58 A 5 6 0001 Assembler Format Op Code R
t ,D
2
(X
2
,B
2
)
L 10,0(5,6) After the instruction is executed,
register 10 contains 00 00 AB CD. LOAD ADDRESS (LA)
The LOAD ADDRESS instruction provides a
convenient way to place a nonnegative
binary integer up to 4095{10} in a
register without first defining a
constant and then using it as an
operand. For example, the following
instruction places the number 2048{10} in register 1:
Machine Format Op Code 41 1 o
o I 800
1 Assembler Format
LA 1,2048(0,0) A-20 System/370 Principles of Operation The LOAD ADDRESS instruction can also be
used to increment a register by an
amount up to 4095{10} specified in the D2 field. Only the rightmost 24 bits of
the sum are retained, however. The
leftmost eight bits of the 32-bit result
are set to zeros. For example, assume
that register 5 contains 00 12 34 56.
The instruction:
Machine Format Op Code R t
41 5 o 5
Assembler Format
LA 5,10(0,5) adds 10 (decimal) to the contents of
register 5 as follows:
Register 5 (old): 00 12 34 56
D2 field: 00 00 00 OA Register 5 (new): 00 12 34 60 The register may be specified as either
B2 or X2. Thus, the instruction LA 5,10(5,0) produces the same result.
As the most general example, the
instruction LA 6,10(5,4) forms the sum
of three values: the contents of regis­
ter 4, the contents of register 5, and a
displacement of 10 and places the 24-bit
sum with eight zeros appended on the
left in register 6. LOAD HALFWORD (LH)
The LOAD unchanged
the right
half of
zeros or
(leftmost
HALFWORD instruction places
a halfword from storage into
half of a register. The left
the register is loaded with
ones according to the sign
bit) of the halfword.
For example, assume that the two bytes
in storage locations 1803-1804 are to be
loaded into register 6. Also assume:
The contents of register 6 are not
significant.
Register 14 contains 00 00 18 03. Locations 1803-1804 contain 00 20. The instruction required to load the
register is: