Decimal &i9h1 Shift
In this example, the contents of storage
location FIELD2 are shifted one place to
the right, effectively dividing the
contents of FIELD2 by 10 and discarding
the remainder. FIELD2 is five bytes in
length. The following instruction
performs this operation:
Machine Format Op Code FO 4
o 1**** I Assembler Format
SRP FIELD2(5),64-1,0 00111111 I 6-bit two's
complement
for -1
FIELD 2 (before): 01 23 45 67 8C
FIELD 2 (after): 00 12 34 56 7C
In the SRP instruction, shifts to the
right are specified in the second­
operand address by negative shift
values, which are represented as a
six-bit value in two's complement form.
The six-bit two's complement of a
number, n, can be specified as 64 -n.
In this example, a right shift of one is
represented as 64 -1.
Condition code 2 is set.
Decimal Right Shift and Round
In this example, the contents of storage
location FIELD3 are shifted three places
to the right and rounded, in effect
dividing by 1000 and rounding up.
FIELD3 is four bytes in length.
Machine Format Op Code FO 3
Assembler Format 00111101 I 6-bit two's
complement
for -3
SRP FIELD3(4),64-3,5
FIELD 3 (before): 12 39 60 OD FIELD 3 (after): 00 01 24 OD The shift amount (three places) is spec­
ified in the D2 field. The 13 field
specifies a rounding digit of 5. The
rounding digit is added to the last
digit shifted out (which is a 6), and
the carry is propagated to the left.
The sign is ignored during the addition.
Condition code 1 is set because the
result is less than zero.
Multiplying g Variable Power of 1Q Since the shift value specified by the
SRP instruction specifies both the
direction and amount of the shift, the
operation is equivalent to multiplying
the decimal first operand by 10 raised
to the power specified by the shift
value.
If the shift value is to be variable, it
may be specified by the B2 field instead
of the displacement D2 of the SRP
instruction. The general register
designated by B2 should contain the
shift value (power of 10) as a signed
binary integer.
A fixed scale factor modifying the vari­
able power of 10 may be specified by
using both the B2 field (variable part
in a general register) and the D2 field
(fixed part in the displacement).
The SRP instruction uses only the right­
most six bits of the effective address
D
2 (B
2
) and interprets them as a six-bit
signed binary integer to control the
left or right shift as in the preceding
shift examples.
Appendix A. Number Representation and Instruction-Use Examples A-35

ZERO AND ADD (ZAP) Assume that the signed, packed-decimal
number at storage locations 4500-4502 is
to be moved to locations 4000-4004 with
four leading zeros in the result field.
Also assume:
Register 9 contains 00 00 40 00. Storage locations 4000-4004 contain 12 34 56 78 90. Storage locations 4500-4502 contain 38 46 ODe After the instruction:
Machine Format Op Code
F8 4 2 9 000 I 9
Assembler Format Op Code Dt(Lt,Bt),D2(L2,B2) ZAP 0(5,9),X'500'(3,9) 500
1 is executed, the storage locations 4000-4004 contain 00 00 38 46 OD; condi­
tion code 1 is set to indicate a nega­
tive result without overflow.
Note that, because the first operand is
not checked for valid sign and digit
codes, it may contain any combination of
hexadecimal digits before the operation. FLOATING-POINT INSTRUCTIONS (See Chapter
tion of the
tions.)
9 for a complete descrip­
floating-point instruc-
In this section, the abbreviations FPRO, FPR2, FPR4, and FPR6 stand for
floating-point registers 0, 2, 4, and 6
respectively.
ADD NORMALIZED (AD, ADR, AE, AER, AXR)
The ADD NORMALIZED instruction performs
the addition of two floating-point
numbers and places the normalized result
in a floating-point register. Neither
of the two numbers to be added must
necessarily be in normalized form before
addition occurs. For example, assume
that: FPR6 contains the unnormalized number C3 08 21 00 00 00 00 00 = -82.1{16}
= -130.06{10} approximately.
Storage locations 2000-2007 contain the
normalized number 41 12 34 56 00 00 A-36 System/370 Principles of Operation 00 00 = +1.23456{16} = +1.14{10} approximately.
Register 13 contains 00 00 20 00. The instruction:
Machine Format Op Code
7A 6 o D 0001 Assembler Format Op Code Rt,D
2
(X
2
,B
2
)
AE 6,0(0,13) performs the short-precision addition of
the two operands, as follows.
The characteristics of the two numbers
(43 and 41) are compared. Since the
number in storage has a characteristic
that is smaller by 2, it is right­
shifted two hexadecimal digit positions. One guard digit is retained on the
right. The fractions of the two numbers
are then added algebraically: FPR6 Shifted number from
storage
Intermediate sum
Left-shifted sum
1 Guard digit
Fraction GDl
-43 08 21 00 +43 00 12 34 5
-43 08 OE CB B
-42 80 EC BB
Because the intermediate sum is unnor­
malized, it is left-shifted to form the
normalized floating-point number -80.ECBB{16} = -128.92{10} approxi­
mately. Combining the sign with the
characteristic, the result is C2 80 EC BB, which replaces the left half of FPR6. The right half of FPR6 and the
contents of storage locations 2000-2007 are unchanged. Condition code 1 is set
to indicate a result less than zero.
If the long-precision instruction AD
were used, the result in FPR6 would be
C2 80 EC BA AO 00 00 00. Note that use
of the long-precision instruction would
avoid a loss of precision in this exam­
ple.
ADD UNNORMALIZED (AU, AUR, AW, AWR)
The ADD UNNORMALIZED instruction oper­
ates the same as the ADD NORMALIZED instruction, except that the final
result is not normalized. For example,
using the the same operands as in the
example for ADD NORMALIZED, when the
short-precision instruction: