R t 1////////1 First-Operand Address 0 8 31
R t + 1 1////////1 First-Operand Length 0 8 31 R2 1////////1 Second-Operand Addressl 0 8 31 R2 + 1
Pad Second-Operand Length 0 8 31
The movement starts at the left end of
both fields and proceeds to the right.
The operation is ended when the number
of bytes specified by bit positions 8-31
of general register Rt + 1 have been
moved into the first-operand location.
If the second operand is shorter than
the first operand, the remaining right­
most bytes of the first-operand location
are filled with the padding byte.
As part of the execution of the instruc­ tion, the values of the two length
fields are compared for the setting of
the condition code, and a check is made
for destructive overlap of the operands.
Operands are said to overlap destruc­
tively when the first-operand location
is used as a source after data has been moved into it, assuming the inspection
for overlap is performed by the use of
logical operand addresses. When the
operands overlap destructively, no move­
ment takes place, and condition code 3
is set. Operands do not overlap destructively,
and movement is performed, if the left­
most byte of the first operand does not
coincide with any of the second-operand
bytes participating in the operation
other than the leftmost byte of the
second operand. When an operand wraps
around from location 16,777,215 to
location 0, operand bytes in locations
up to and including 16,777,215 are
considered to be to the left of bytes in
locations from 0 up.
When the length specified by bit posi­
tions 8-31 of general register RI + 1 is zero, no movement takes place, and
condition code 0 or 1 is set to indicate
the relative values of the lengths.
instruction is The execution of the
interruptible. When occurs other than one
nation, the contents
ters Rt + 1 and R2 +
an interruption
that causes termi­
of general regis-
1 are decremented
by the number of bytes moved, and the
contents of general registers Rt and R2 are incremented by the same number, so
that the instruction, when reexecuted, resumes at the point of interruption. The leftmost bits which are not part of
the address in general registers R, and
R2 are set to zeros; the contents of bit
positions 0-7 of general registers R, + 1 and R2 + 1 remain unchanged; and
the condition code is unpredictable. If
the operation is interrupted during
padding, the length field in general
register R2 + 1 is 0, the address in
general register R2 is incremented by
the original contents of general regis­
ter R2 + 1, and general registers Rt and R, + 1 reflect the extent of the padding
operation.
When the first-operand location includes
the location of the instruction or of
EXECUTE, the instruction may be
refetched from storage and reinterpreted even in the absence of an interruption
during execution. The exact point in
the execution at which such a refetch
occurs is unpredictable.
As observed by other CPUs and by chan­
nels, that portion of the first operand
which is filled with the padding byte is not necessarily stored into in a left­
to-right direction and may appear to be
stored into more than once.
At the completion of the operation, the
length in general register R, + 1 is
decremented by the number of bytes
stored at the first-operand location,
and the address in general register Rt
is incremented by the same amount. The
length in general register R2 + 1 is
decremented by the number of bytes moved
out of the second-operand location, and
the address in general register R2 is
incremented by the same amount. The
leftmost bits which are not part of the
address in general registers R, and R2 are set to zeros, including the case
when one or both of the original length
values are zeros or when condition code
3 is set. The contents of bit positions 0-7 of general registers Rt + 1 and
R2 + 1 remain unchanged.
When condition code 3 is set, no
exceptions associated with operand
access are recognized. When the length
of an operand is zero, no access
exceptions for that operand are recog-
nized. Similarly, when the second
operand is longer than the first
operand, access exceptions are not
recognized for the part of the second­
operand field that is in excess of the
first-operand field. For operands long­
er than 2K bytes, access exceptions are
not recognized for locations more than
2K bytes beyond the current location
being processed. Access exceptions are
not recognized for an operand if the R
field associated with that operand is
odd. Also, when the R, field is odd, Chapter 7. General Instructions 7-25

PER storage-alteration events are not
recognized, and no change bits are set. 0 Operand lengths equal; no
destructive overlap
1 First-operand length low; no
destructive overlap
2 First-operand length high; no
destructive overlap
3 No movement performed because
of destructive overlap
Program Exceptions:
Access (fetch, operand 2;
operand 1)
Specification
store,
Programming Notes
1 . An example of the use of the MOVE LONG instruction is given in Appen­
dix A.
2. MOVE LONG may be used for clearing
storage by setting the padding byte
to zero and the second-operand
length to zero. On most models,
this is the fastest instruction for
clearing storage areas in excess of
256 bytes. However, the stores
associated with this clearing may
be multiple-access stores and
should not be used to clear an area
if the possibility exists that
another CPU or a channel will
attempt to access and use the area as soon as it appears to be zero. For more details, see the section "Storage-Operand Consistency" in Chapter 5, "Program Execution." 3. The program should avoid specifica­
tion of a length for either operand
which would result in an addressing
exception. Addressing (and also
protection) exceptions may result
in termination of the entire opera­
tion, not just the current unit of
operation. The termination may be
such that the contents of all
result fields are unpredictable; in
the case of MOVE LONG, this
includes the condition code and the
two even-odd general-register
pairs, as well as the first-operand
location in main storage. The
following are situations that have
actually occurred on one or more
models:
a. When a protection exception
occurs on a 2K-byte block, or,
when the storage-key 4K-byte­
block facility is installed, on a 4K-byte block, of a first
operand which is several blocks
in length, stores to the
protected block are suppressed.
7-26 System/370 Principles of Operation 4.
b.
However, the move continues
into the subsequent blocks of
the first operand, which are
not protected. Similarly, an
addressing exception on a block
does not necessarily suppress
processing of subsequent blocks
which are available. Some models may update the
general registers only when an
external, I/O, repressible
machine-check, or restart
interruption occurs, or when a program interruption occurs for
which it is required to nullify
or suppress a unit of
operation. Thus, if, after a move into several blocks of the
first operand, an addressing or
protection exception occurs,
the general registers may
remain unchanged.
When the first-operand length
zero, the operation consists
setting the condition code
setting the leftmost bytes
general registers R\ and R2 zero.
i s
in
and
of
to
5. When the contents of the Rt and R2 fields are the same, the operation
proceeds the same way as when two
distinct pairs of registers having
the same contents are designated. Condition code 0 is set.
6. The. following is a detailed
description of those cases in which
movement takes place, that is,
where destructive overlap does not
exist. Depending on whether the
second operand wraps around from
location 224 -1 to location 0, movement takes place in the follow­
ing cases: a. When the second operand does
not wrap around, movement is
performed if the leftmost byte
of the first operand coincides
with or is to the left of the
leftmost byte of the second
operand, or if the leftmost
byte of the-first operand is to
the right of the rightmost
second-operand byte participat­
ing in the operation.
b. When the second operand wraps
around, movement is performed
if the leftmost byte of the
first operand coincides with or
is to the left of the leftmost
byte of the second operand, and
if the leftmost byte of the
first operand is to the right
of the rightmost second-operand
byte participating in the oper­
ation.
The rightmost second-operand byte
is determined by using the smaller