CHAPTER STORAGE Storage Addressi ng .....•.....•.....•••••..••••..•.....•.•• 3-2
Storage Addressing with Extended Address Fields ..••... 3-3
Information Formats ....•................•....•.......... 3-3
Integral Boundaries ..............••........••........... 3-3 Byte-Oriented-Operand Facility ••..•.•••...••..••••...••. 3-5
Address Types .............•..•.••.•...••...•.•.•••...•••.• 3-5
Absolute Address ....•...•..••••...••.....•••..•....••. 3-5
Real Address ...........•.....•....•......•••.•.••.•.•. 3-5
Virtual Address ........•....••..•.....•...••..••..•... 3-5
Primary Virtual Address •...•..•.•.....•...•••.•••.•.•. 3-5
Secondary Virtual Address ..•••....•••...••••.••.•..•.. 3-6 Logi cal Address ....................................... 3-6
Instruction Address ....•....••.............•......•... 3-6
Effective Address ....••••...•••...•.•....••..•.•.•••.. 3-6
Storage Key ..........................••......•..••........ 3-6
Storage-Key 4K-Byte-Block Fac iIi ty •..........•..•.•••... 3-7
Storage Keys with Storage-Key 4K-Byte-Block
Facility Not Installed ........••..........•.•••••.•.. 3-7
Storage Keys with Storage-Key 4K-Byte-Block Facility Installed ......•..........•.•.....••.••..... 3-7
Storage-Key-Exception Control .........•...•........... 3-7
Storage-Key-Instruction Extensions .........•......•.•... 3-7
Protection ...•..................•.....•......•...•....••.. 3-7 Key-Controlled Protection .....•.•.•..••...••.•.••.....•. 3-8
Segment Protection ........•.........•••.•.•••.••••...••. 3-9
low-Address Protection ..................•...••...•...••. 3-9
Reference Recording .........••.......•....••..•.•...•••.•. 3-10 Change Recording ........•.................••...•.....•.... 3-10 Prefixing .........................•...•...••.......•...... 3-11
Address Spaces .......•..............•...•...............•. 3-12 ASH Translation ...•.•....••.....•.•.•••.•...•.......•..... 3-13
ASH-Translation Controls ..•......•.........••...••.••••. 3-13 ASH-Translation Tables .............••.•....••.......••.. 3-14 ASH-First-Table Entries ...........•...•..••...•...•.•. 3-14
ASN-Second-Table Entries ..................•....•.•..•. 3-14
ASH-Translation Process ..••.•....••...•.•...•••.•.•...•. 3-15 ASH-First-Table Lookup ........•....................... 3-16
ASH-Second-Table lookup .•...........•.•.•...•.••...... 3-16
Recognition of Exceptions during ASH Translation ...... 3-17 ASH Authorization ...............•.....•.•.............•... 3-17
ASH-Authorization Controls ...•.•....••....•...•....••... 3-17 Control Register 4 ....•.....•....••••.•.•....••.•••.•. 3-17
ASN-Second-Table Entry ...........••......•...••..••... 3-17
Authority-Table Entries ...........•................... 3-18
ASH-Authorization Process •••••..•.••....•...•••.••••.••. 3-18
Authority-Table lookup •••.•..•..••....•••••••.•••.•••• 3-19
Recognition of Exceptions during ASH Authorization •.......•...•••...•..••...•..••••.••.••• 3-20 Dynamic Address Translation ..••....••••....•...•..••••.••• 3-20 Translation Control .•.••••••••••••..•••.•••••.•..••.•.•• 3-22
Translation Modes .••••...•....•.•••.•..••.•••.•..••..• 3-22 Control Register 0 •.•...•.......•••...•.••..•...••.... 3-23 Control Register 1 ..••..•.•.•.•.....•....•....•.••.•.. 3-24 Control Register 7 ..•••.••.••.•••••••.••••.••••••.•••. 3-24
Translation Tables •...•.••.••••....••••.•••••.••.••••..• 3-25
Segment-Table Entries ...•..•••..••••••..•.•.••.••.••.. 3-25
Page-Table Entries ..•..•...••.•.•••••....•..••.••••••• 3-26
Summary of Dynamic-Address-Translation Formats ••••.••••• 3-26
Translation Process ••.•.•.••..•••.••••••••.••••••••••••. 3-27
Effective Segment-Table Designation ••.••.•.•.••••••••. 3-27
Inspecti on of Control Regi ster 0 •••••......•••.....••. 3-30 Segment-Table lookup ••........•..•....•.............•. 3-30 Page-Table lookup •••.•.••.•••••••••••.•••••••••••••.•• 3-31
Formation of the Real Address ••••••••••••••••..•.••••. 3-31
Recognition of Exceptions during Translation •••••••••• 3-31
Translation-lookaside Buffer .•...•••..•..••..•••••.••••• 3-31
Use of the Translation-lookaside Buffer ••••••••••••••• 3-32
Modification of Translation Tables •••••••••••••••••••• 3-36 Chapter 3. Storage 3-1

Address Summary ••.•••••.••...•..•••••••••.••••.•...•.••••• 3-38
Addresses Translated .•••••.••...••..••......•......•.... 3-38 Handling of Addresses •.•.•...•..•••.•••••..•••.••...•.•. 3-39
Assigned Storage locations .........•••..•.•.......•....••. 3-41
This chapter discusses the represen­
tation of information in main storage, as well as addressing, protection, and
reference and change recording. The aspects of addressing which are covered
include the format of addresses, the
concept of address spaces, the various
types of addresses, and the manner in
which one type of address is translated
to another type of address. A list of
permanently assigned storage locations
appears at the end of the chapter.
Main storage provides the system with
directly addressable fast-access storage
of data. Both data and programs must be loaded into main storage (from input
devices) before they can be processed.
Main storage may include one or more
smaller faster-access buffer storages,
sometimes called caches. A cache 1S
usually physically associated with a CPU or an I/O processor. The effects,
except on performance, of the physical
construction and use of distinct storage media are not observable by the program.
Fetching and storing of data by a CPU are not affected by any concurrent chan­
nel activity or by a concurrent refer­
ence to the same storage location by
another CPU. When concurrent requests
to a main-storage location occur, access
normally is granted in a sequence that
assigns highest priority to references by channels, the priority being rotated
among CPUs. If a reference changes the
contents of the location, any subsequent
storage fetches obtain the new contents.
Main storage may be volatile or nonvola­
tile. If it is volatile, the contents
of main storage are not preserved when
power is turned off. If it is nonvola­
tile, turning power off and then back on
does not affect the contents of main
storage, provided all CPUs are in the
stopped state and no references are made
to main storage when power is being
turned off. In both types of main stor­ age, the contents of the storage key are
not necessarily preserved when the power
for main storage is turned off.
Note: Because most references in this
pUblication apply to virtual storage,
the abbreviated term "storage" is often
used in place of "virtual storage." The
term "storage" may also be used in place
of "main storage," "absolute storage,"
or "real storage" when the meaning is
clear. The terms "main storage" and
"absolute storage" are used to describe
storage which is addressable by means of
3-2 System/370 Principles of Operation an absolute address. The terms describe
fast-access storage, as opposed to
auxiliary storage, such as provided by
direct-access storage devices. "Real
storage" is synonymous with "absolute
storage" except for the effects of
prefixing. STORAGE ADDRESSING
Storage is viewed as a long horizontal
string of bits. For most operations,
accesses to storage proceed in a left­
to-right sequence. The string of bits is subdivided into units of eight bits.
An eight-bit unit is called a byte,
which is the basic building block of all
information formats.
Each byte location in storage is identi­
fied by a unique nonnegative integer,
which 1S the address of that byte
location or, simply, the byte address.
Adjacent byte locations have consecutive
addresses, starting with 0 on the left
and proceeding in a left-to-right
sequence. With the exception of those
facilities described in "Storage Addressing with Extended Address Fields" below, addresses are 24-bit unsigned binary integers, which provide
16,777,216 (2
24
or 16M) byte addresses.
The CPU performs address generation when
it forms an operand or instruction
address, or when it generates the
address of a table entry from the appro­
priate table origin and index. It also
performs address generation when it
increments an address to access succes­
sive bytes of a field. Similarly, the
channel performs address generation when
it increments an address (1) to fetch a CCW, (2) to fetch an IDAW or (3) to
transfer data. When, during address generation, an
address is obtained that exceeds
224 -1, the carry out of the leftmost
bit position of the address is ignored.
This handling of an address of excessive
size is called wraparound.
The effect of wraparound is to make the
sequence of addresses appear circular;
that is, address 0 appears to follow the
maximum byte address, 16,777,215.
Address arithmetic and wraparound occur
before transformation, if any, of the
address by dynamic address translation
or prefixing. With a 16M-byte storage,
information may be located partially in