ADDRESS GENERATION Execution of instructions by the CPU involves generation of the addresses of instructions and operands. This section describes address generation as it applies to most instructions. In some
instructions, theoperation performed
does not follow the general rules stated
inthis section. All of these exceptions are explicitly identified in
the individual instruction descriptions.SEQUENTIAL INSTRUCTION-ADDRESS GENER ATION When an instruction is fetched from the
location designated by the currentPSW, the instruction address is increased by
the number of bytes in the instruction,
andthe instruction is executed. The same steps are then repeated by using
the new value of the instruction address
to fetch thenext instruction in the
sequence.
Instruction addresses wrap around, with
the halfword at instruction address224 - 2 being followed by the halfword
at instruction address o. Thus, any
carry out ofPSW bit position 40, as a result of updating the instruction
address, is lost.OPERAND-ADDRESS GENERATION An operand address that refers to stor age either is contained in a register designated by an R field in the instruc
tion or is calculated from the sum ofthree binary numbers: base address, index, and displacement.
The base address(n) is a 24-bit number
contained ina general register speci fied by the program in a four-bit field,
called the B field, in the instruction.
Base addresses canbe used as a means of
independently addressing each program
and data area. In array-type calcu
lations,it can designate the location
of an array, and, in record-type proc
essing, it can identify the record. The
base address provides for addressing the
entire storage. The base address may
also be used for indexing.
The index (X) isa 24-bit number
contained ina general register desig nated by the program in a four-bit field, called the X field, in the
instruction. It is included onlyin the
address specified by the RX-format
instructions. The RX-format instruc-
tions permit double indexing; that is,
the index canbe used to provide the
address of anelement within an array.
The displacement (D) isa 12-bit number contained in a field, called the D
field,in the instruction. The
displacement provides for relative
addressing of up to4,095 bytes beyond
the location designated by the base
address. In array-type calculations,
the displacement can be used to specifyone of many items associated with an
element. In the processing of records,the displacement can be used to identify
items withina record.
In forming the address,the base address
and index are treated as 24-bitbinary integers. The displacement is similarly
treated as a 12-bit unsignedbinary integer, and 12 zeros are appended on
the left. The three are added as 24-bit
binary numbers, ignoring overflow. The
sum is always 24bits long. The bits of
the generated address are numbered 8-31,
corresponding to the numbering of the
base-address and index bits in the
general register.
A zero in any of the Bt,B21 or X 2 fields indicates the absence of the
corresponding address component. For
the absent component, a zero is used in
forming the address, regardless of the
contents of general registerO. A
displacement of zero has no special
significance.
When an instruction description specifies that the contents of a general
register designated by an R field are
used to address an operandin storage,
bit positions 8-31 of the register
provide the operand address. For the
instructions INSERTSTORAGE KEY
EXTENDED, RESETREFERENCE BIT EXTENDED,
SETSTORAGE KEY EXTENDED, and TEST BLOCK, bits 1-31 of the register provide the address.
An instruction can designate the same
general register both for address computation and as the location of an
operand. Address computationis completed before registers, if any, are changed by the operation. Unless otherwise indicated in an indi
vidual instruction definition, the
generated operand addressdesignates the
leftmost byte of an operand in storage.Programming Note Negative values may be used in index and
base-address registers.Bits 0-7 of these values are always ignored.
Chapter 5. Program Execution 5-5
instructions, the
does not follow the general rules stated
in
the individual instruction descriptions.
location designated by the current
the number of bytes in the instruction,
and
the new value of the instruction address
to fetch the
sequence.
Instruction addresses wrap around, with
the halfword at instruction address
at instruction address o. Thus, any
carry out of
address, is lost.
tion or is calculated from the sum of
The base address
contained in
called the B field, in the instruction.
Base addresses can
independently addressing each program
and data area. In array-type calcu
lations,
of an array, and, in record-type proc
essing, it can identify the record. The
base address provides for addressing the
entire storage. The base address may
also be used for indexing.
The index (X) is
contained in
instruction. It is included only
address specified by the RX-format
instructions. The RX-format instruc-
tions permit double indexing; that is,
the index can
address of an
The displacement (D) is
field,
displacement provides for relative
addressing of up to
the location designated by the base
address. In array-type calculations,
the displacement can be used to specify
element. In the processing of records,
items within
In forming the address,
and index are treated as 24-bit
treated as a 12-bit unsigned
the left. The three are added as 24-bit
binary numbers, ignoring overflow. The
sum is always 24
the generated address are numbered 8-31,
corresponding to the numbering of the
base-address and index bits in the
general register.
A zero in any of the Bt,
corresponding address component. For
the absent component, a zero is used in
forming the address, regardless of the
contents of general register
displacement of zero has no special
significance.
When an instruction description speci
register designated by an R field are
used to address an operand
bit positions 8-31 of the register
provide the operand address. For the
instructions INSERT
EXTENDED, RESET
SET
An instruction can designate the same
general register both for address compu
operand. Address computation
vidual instruction definition, the
generated operand address
leftmost byte of an operand in storage.
base-address registers.
Chapter 5. Program Execution 5-5