determine if the address space can be
established as a secondary address
space. The tested bit must be one;
otherwise, a secondary-authority excep­
tion is recognized.
The instruction PROGRAM TRANSFER with
space switching uses the authorization
index to test the primary authority bit
in the authority-table entry to deter­
mine if the address space can be estab­
lished as a primary address space. The
tested bit must
primary-authority
nized.
be one; otherwise, a
exception is recog-
The instruction PROGRAM CALL with space
switching causes a new authorization
index to be loaded from the ASN-second­
table entry. This permits the program
which is called to be given an authori­
zation index which authorizes it to
access more address spaces than those
authorized for the calling program. Chapter 5. Program Execution 5-19
Authorization Mechanism
A5N- P5W- 5pace-
Mode Translation-Key Mask Switch-
Requirement Subsystem-5econdary-Control Extraction-(CR3.0-1S) Authori-Event-
linkage Space (CR14.12) Authority zation Control Priv Trans Control Control Control Bit AND Index Bit
Instr Op Mode (CR5.0) (CRO.S) Un cd Cond (CRO.4) Test AKMI (CR4.0-1S) (CRl. 31> EPAR 50-PS Q
ESAR SO-PS Q lAC 50-PS Q IPK Q
IVSK 50-P5 Q lASP P 50 CC CC £,1VCP SO-PS 50 Q
MVCS SO-PS SO Q
MVCK Q PC-cp 50-P SO Q PC-ss 50-P 50 50 Q PT-cp Q2 SO-P 50 PT-ss Q2 50-P 50 50 PA SAC SO-P5 SO 5PKA Q
55AR-cp 50-P5 50
55AR-ss SO-P5 50 SA
Explanation: 2 The P5W-key mask is ANDed with the authorization key mask in the entry-table entry.
The exception is recognized on an attempt to set the supervisor state when in the
problem state.
X
X
CC 5pace-switch-event-control bit and authorization index tests cause a condition code to
be set.
CRx.y P PA Control register x, bit position y. Privileged-operation exception for privileged instruction.
Authority checked in both the problem and supervisor states; violation causes a
primary-authority exception.
Q Privileged-operation exception for semiprivileged instruction. Authority checked only in the problem state.
5A Authority checked in both the problem and supervisor states; violation causes a
secondary-authority exception.
50 Authority checked in both the problem and supervisor states; violation causes a
special-operation exception. 50-P CPU must be in the primary-space mode; if the CPU is in the secondary-space mode or
in the real mode, a special-operation exception is recognized in both the problem and
supervisor states. 50-PS CPU must be in the primary-space mode or the secondary-space mode; if the CPU is in
the real mode. a special-operation exception is recognized in both the problem and
supervisor states.
X When bit 31 of control register 1 is one, a space-switch event is recognized. The
operation is completed. The event is recognized in both the problem and supervisor
states.
Summary of DAS Authorization Mechanisms 5-20 System/370 Principles of Operation
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