Programming Note The independent fetching of a single
location for each of two operands may
affect the program execution in the
following situation.
When the same storage location is desig­ nated by two operand addresses of an
instruction, and another CPU or a chan­
nel causes the contents of the location
to change during execution of the
instruction, the old and new values of the location may be used simultaneously.
For example, comparison of a field to
itself may yield a result other than
equal, or EXCLUSIVE-ORing of a field
with itself may yield a result other than zero. OTHER STORAGE REFERENCES The resta rt, program, superv i so r-ca 11, external, input/output, and mach; ne­ check PSWs appear to be accessed doubleword-concurrent as observed by other CPUs. Those references appear to
occur after the conceptually previous unit of operation and before the concep­
tually subsequent unit of operation. The relationship between the new-PSW fetch, the old-PSW store, and the
interruption-code store is unpredic­
table. Store accesses for interruption codes
not stored within the old PSW are not
necessarily single-access stores. The
store accesses for the external and
supervisor-calI-interruption codes
appear to occur between the conceptually
previous and conceptually subsequent
operations. The store accesses for the program-interruption codes may precede the storage-operand references associ­
ated with the instruction which results
in the program interruption.
The stores into the CSW and 1/0- communication area occur within the
conceptual limits of the interruption or I/O instruction with which they are associated.
Updating of the interval timer occurs
after storage-operand references for the
conceptually prevl0us instruction and before storage-operand references for the conceptually subsequent instruction.
Interval-timer updates can also occur
within an interruptible instruction between units of operation. SERIALIZATION Th2 sequence of functions performed by a CPU is normally independent of the func-
tions performed by other CPUs and by
channels. Similarly, the sequence of
functions performed by a channel is normally independent of the functions
performed by other channels and by CPUs. However, at certain points in its
execution, serialization of the CPU occurs. Serialization also occurs at
certain points for channel programs.
CPU SERIALIZATION All interruptions and the execution of
certain instructions cause a serializa­
tion of CPU operations. A serialization
operation consists in completing all
conceptually previous storage accesses
by the CPU, as observed by other CPUs and by channels, before the conceptually
subsequent storage accesses occur. Serialization affects the sequence of
all CPU accesses to storage and to the
storage keys, except for those associ­
ated with DAT-table-entry fetching. Serialization is performed by CPU reset,
all interruptions, and by the execution
of the following instructions! • The general instructions BRANCH ON CONDITION (BCR) with the M t and R2 field containing all ones and all
zeros, respectively, and COMPARE AND SWAP, COMPARE DOUBLE AND SWAP, STORE CLOCK, SUPERVISOR CALL, and
TEST AND SET. • • • • • LOAD PSW, SET STORAGE KEY, and SET STORAGE KEY EXTENDED.
All I/O instructions, CONNECT CHAN­
NEL SET, and DISCONNECT CHANNEL SET. PURGE TLB and SET PREFIX, which
also cause the translation­
lookaside buffer to be cleared of
entries. SIGNAL PROCESSOR, READ DIRECT, and L,JR IT E D IRE CT.
INVALIDATE PAGE TABLE ENTRY. • TEST BLOCK. • • MOVE TO PRIMARY, MOVE TO SECONDARY, PROGRAM CALL, PROGRAM TRANSFER, SET
ADDRESS SPACE CONTROL, and SET SECot~DARY ASN. The DAS-tracing function causes
serialization to be performed before the trace action and after
completion of the trace action. The sequence of events associated with a
serializing operation is as follows:
1. All conceptually previous storage
accesses by the CPU are completed
Chapter 5. Program Execution 5-33

as observed by other CPUs and by
channels. This includes all
conceptually previous stores and
changes to the storage keys.
2. The normal function associated with the serializing operation is
performed. In the case of instruc­
tion execution, operands are fetched, and the storing of results
is completed. The exceptions are LOAD PSW and SET PREFIX, in which
the operand may be fetched before
previous stores have been
completed, and interrupti ons, in
which the interruption code and associated fields may be stored
prior to the serialization. The
fetching of the serializing
instruction occurs before the
execution of the instruction and
may precede the execution of previ­
ous instructions, but may not precede the completion of any
previous serializing op~ration. In the case of an interruption, the old PSW, the interruption code, and other information, if any, are stored, and the new PSW is fetched,
but not necessarily in that sequence. 3. Finally, instruction fetch and
operand accesses for conceptually
subsequent operations may begin.
A serializing function affects the
sequence of storage accesses that are
under the control of the CPU in which
the serializing function takes place.
It does not affect the sequence of stor­
age accesses under the control of other CPUs and of channels. Programming Notes
1. The following are some effects of a serializing operation: a. When the execution of an
instruction changes the
contents of a storage location
that is used as a source of a following instruction and when
different addresses are used to designate the same absolute
location for storing the result
and fetching the instruction, a serializing operation following
the change ensures that the
5-34 System/370 Principles of Operation modified
executed.
instruction is
b. When a serializing operation
takes place, other CPUs and
channels observe instruction
and operand fetching and result
storing to take place in the
sequence established by the
serializing operation.
2. Storing into a location from which a serializing instruction is
fetched does not necessarily affect
the execution of the serializing
instruction unless a serializing
function has been performed after
the storing and before the
execution of the serializing
instruction. CHANNEL-PROGRAM SERIALIZATION Serialization of a channel
occurs as follows:
program
1. All storage accesses and storage­
key accesses by the channel program
follow initiation of the execution
of START I/O or START I/O FAST
RELEASE, or, if suspended, RESUME I/O, as observed by CPUs and by
other channels. This includes all
accesses for the CAW, CCWs, IDAWs,
and data. 2. All storage accesses and storage­
key accesses by the channel program
are completed, as observed by CPUs and by other channels, before the CSW is stored indicating termi­
nation of the operation at the
subchannel.
3. If a CCW contains a PCI flag or a
suspend flag which is one, all
storage accesses and storage-key
accesses due to CCWs preceding it in the CCW chain are completed, as
observed by CPUs and by other chan­
nels, before the CSW is stored
indicating the PCI or suspended
condition.
The serialization of a channel program
does not affect the sequence of storage accesses or storage-key accesses caused
by other channel programs or by another CPU program.