Resulting Condition Code: Result zero; no overflow o
1
2 Result greater than zero; no
overflow
3 Overflow
Program Exceptions:
Fixed-point overflow
Programming Note The operation complements negative
numbers; positive numbers and zero
remain unchanged. An overflow condition
occurs when the maximum negative number
is complemented; the number remains
unchanged. MONITOR CAll MC [SI]
'AF' D, o 8 16 20 31
A program interruption is caused if the
appropriate monitor-mask bit in control
register 8 is one.
The monitor-mask bits are in bit posi­
tions 16-31 of control register 8, which
correspond to monitor classes 0-15, respectively.
Bit positions 12-15 in the 12 field
contain a binary number specifying one
of 16 monitoring classes. When the
monitor-mask bit corresponding to the
class specified by the 12 field is one,
a monitor-event program interruption
occurs. The contents of the 12 field
are stored at location 149, with zeros
stored at location 148. Bit 9 of the
program-interruption code is set to one.
The first-operand address is not used to
address data; instead, the address spec­
ified by the B, and D, fields forms the
monitor code, which is placed in the
word at location 156. Address computa­
tion follows the rules of address
arithmetic; bits 0-7 are set to zeros.
When the monitor-mask bit corresponding
to the class specified by bits 12-15 of
the instruction is zero, no interruption
occurs, and the instruction is executed
as a no-operation.
Bit positions 8-11 of the instruction
must contain zeros; otherwise, a spec­
ification exception is recognized. Condition Code: unchanged.
The code remains
Program Exceptions:
Monitor event
Specification
Programming Notes
1. MONITOR CAll provides the capabili­
ty for passing control to a moni­
toring program when selected points
are reached in the monitored
program. This is accomplished by
implanting MONITOR CALL instructions at the desired points
in the monitored program. This
function may be useful in perform­
ing various measurement functions;
specifically, tracing information
can be generated indicating which
programs were executed, counting
information can be generated indi-
cating how often particular
programs were used, and timing
information can be generated indi­
cating how long a particular
program required for execution.
2. The monitor masks provide a means
of disallowing all monitor-event
program interruptions or "allowing
monitor-event program interruptions
for all or selected classes.
3. The monitor code provides a means
of associating descriptive informa­
tion, in addition to the class
number, with each MONITOR CALL. Without the use of a base register,
up to 4,096 distinct monitor codes
can be associated with a monitoring
interruption. With the base regis­
ter designated by a nonzero value
in the Bl field, each monitoring
interruption can be identified by a
24-bit code.
MOVE
MVI 0\(B\),I
2
[SI] 0, o 8 16 20 31
[SS] '02' L I s, I B2 I o 8 16 20 32
The second operand is placed
first-operand location.
36 47
at the Chapter 7. General Instructions 7-23
For MOVE (MVC), each operand is proc­ essed left to right. When the operands overlap, the result is obtained as if
the operands were processed one byte at
a time and each result byte were stored
immediately after fetching the necessary
operand byte.
For MOVE (MVI), the first operand is one
byte in length, and only one byte is
stored. Condition Code: unchanged.
The code remains Program Exceptions:
Access (fetch, operand 2 of MVC; store, operand 1, MVI and MVC) Programming Notes
1 .
2.
Examples of the use
instruction are given
A.
of the MOVE in Appendix
It is possible to propagate one
byte through an entire field by
having the first operand start one
byte to the right of the second
operand. MOVE INVERSE [SS] 'E8' l I B, I B, I o 8 16 20 32 36 47
The second operand is placed at the
first-operand location with the left­
to-right sequence of the bytes inverted.
The first-operand address designates the
leftmost byte of the first operand. The
second-operand address designates the
rightmost byte of the second operand.
Both operands have the same length.
The result is obtained as if the second
operand were processed from right to
left and the first operand from left to
right. The second operand may wrap
around from location 0 to location
224 -1. The first operand may wrap
around from location 224 - 1 to location
o.
When the operands overlap by more than
one byte, the contents of the overlapped
portion of the result field are unpre­
dictable. Condition Code: unchanged.
The code remains
7-24 System/370 Principles of Operation Program Exceptions:
Access (fetch, operand 2; store, operand 1) Operation (if the move-inverse facility is not installed) Programming Notes
1. An example of the use of the MOVE INVERSE instruction is given in Appendix A.
2. The contents of each byte moved
remain unchanged.
3. MOVE INVERSE is the only SS-format instruction for which the second­
operand address designates the
rightmost, instead of the leftmost,
byte of the second operand.
4. The storage-operand references for MOVE INVERSE may be multiple-access
references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") MOVE LONG MveL [RR] 'OE' o 8 12 15
The second operand is placed at the
first-operand location, provided over­
lapping of operand locations would not
affect the final contents of the first­
operand location. The remaining right­
most byte positions, if any, of the
first-operand location are filled with
padding bytes.
The Rt and R2 fields each
even-odd pair of general
must designate an regi ster; otherwi se, a
exception is recognized.
designate an
registers and
even-numbered
specification
The location of the leftmost byte of the
first operand and second operand is
designated by bits 8-31 of general
registers Rt and R
2
,
respectively. The
number of bytes in the first-operand and second-operand locations is specified by
bits 8-31 of general registers Rt + 1
and R2 + I, respectively. Bit positions 0-7 of register R2 + 1 contain the
padding byte. The contents of bit posi­
tions 0-7 of registers Rt, R
2
,
and
R t + 1 are ignored.
The contents of the registers just
described are as follows:
Previous Page Next Page