1.-6. Exceptions with the same pri­
ority as the priority of pro­
gram-interruption conditions
for the general case.
7.A Access exceptions for second
instruction halfword.
7.B.1 Operation exception if the dual-address-space facility is
not installed.
7.B.2 Special-operation exception due to OAT being off.
8.
9. Privileged-operation exception due to extraction-authority control, bit 4 of control reg­ ister 0, being zero.
Access exceptions (except for
protection) for address speci­
fied by general register R 2 . Priority of Execution: INSERT VIRTUAL STORAGE KEY Programming Note Since all bytes in a 2K-byte block are associated with the same page and the
same storage key, bits 21-31 of general
register R2 effectively are ignored.
When 4K-byte pages are used, the
storage-key 4K-byte-block facility is installed, and all blocks are single-key
4K-byte blocks, then bits 20-31 of
general register R2 essentially are
ignored.
INVALIDATE PAGE TABLE ENTRY IPTE [RRE]
'B221' 1////////1 R, o 16 24 28 31
The designated page-table entry is invalidated, and the translation­
lookaside buffers (TLBs) in all CPUs in
the configuration are cleared of the
associated entries.
Bits 16-23
ignored.
of the instruction are
The contents of general register R t have
the format of a segment-table entry with
only the page-table origin used. The
contents of general register R2 have the
format of a virtual address with only
the page index used. The contents of
fields that are not part of the page­
table origin or page index are ignored.
The translation format, contained in bit
positions 8-12 of control register 0, specifies the mode for translation.
The contents of the general registers
just described are as follows: R t 1////////1 Page-Table Origin 1///1 o 8 29 31 R2 (for 64K-byte segments and 4K-byte
pages)
1////////////////1 PX 1////////////1 o 16 20 31 R2 (for 64K-byte segments and 2K-byte
pages) 1////////////////1 PX 1///////////1 o 16 21 31 R2 (for 1M-byte segments and 4K-byte
pages) 1////////////1 PX 1////////////1 o 12 20 31 R2 (for 1M-byte segments and 2K-byte
pages) 1////////////1 PX 1///////////1 o 12 21 31
The page-table origin and the page index
designate a page-table entry, following
the dynamic-address-translation rules
for page-table lookup. The address
formed from these two components is a
real address. The page-invalid bit of
this page-table entry is set to one.
During this procedure, no page-table­
length check is made, and the page-table
entry is not inspected for availability
or format errors. Additionally, the
page-frame real address (including the
extended-addressing bits, when applica­
ble) contained in the entry is not
checked for an addressing exception.
The entire page-table entry is fetched
concurrently from storage. Subsequently
the byte containing the page-invalid bit
is stored. The fetch access to the
page-table entry is subject to key­
controlled protection, and the store
Chapter 10. Control Instructions 10-11

access is subject to key-controlled
protection and low-address protection.
A serialization function is performed
before the operation begins and again after the operation is completed. As is
the case for all serialization oper­ ations, this serialization applies only
to this CPU; other CPUs are not neces­
sarily serialized.
If it is successful in setting the
page-invalid bit to one, this CPU clears
selected entries from its TLB and
signals all CPUs in the configuration to
clear selected entries from their TLBs.
Each TLB is cleared of at least those
entries that have been formed using all
of the following: • The translation format specified in
bit positions 8-12 of control
register 0 of the CPU executing the
INVALIDATE PAGE TABLE ENTRY instruction • The page-table orlgln designated by
the first operand • The page index designated by the
second operand • The page-frame real address
(including the extended-addressing bits, when applicable) contained in
the designated page-table entry
The execution of INVALIDATE PAGE TABLE ENTRY is not completed on the CPU which
executes it until (1) all entries corre­
sponding to the specified parameters
have been cleared from the TLB on this CPU and (2) all other CPUs in the
configuration have completed any storage accesses, including the updating of the
change and reference bits, by using TLB
entries corresponding to the specified
parameters.
Special Conditions When bit positions 8-12 of control
register 0 contain an invalid code, a
translation-specification exception is
recognized. The exception is recognized
regardless of whether DAT is on or off.
The operation is suppressed on all
addressing and protection exceptions. Condition Code: unchanged.
Program Exceptions:
The code remains
Addressing (page-table entry)
Operation (if the extended facility
is not installed)
Privileged operation
Protection (fetch and store, page­
table entry, key-controlled 10-12 System/370 Principles of Operation protection, and low-address
protection)
Translation specification (bits
8-12 in control register 0 only)
Programming Notes
1. The selective clearing of entries
may be implemented in different ways, depending on the model, and, in general, more entries may be
cleared than the mlnlmum number
required. Some models may clear all entries which contain the
designated page-frame real address.
Others may clear all entries which
contain the designated page index,
and some implementations may clear
precisely the minimum number of
entries required. Therefore, in
order for a program to operate on
all models, the program should not
take advantage of any properties
obtained by a less selective clear­
ing on a particular model.
2. The clearing of TLB entries may
make use of the page-frame real
address in the page-table entry.
Therefore, if the page-table entry,
when in the attached state, ever
contained a page-frame real address
that is different from the current
value, copies of the previous
values may remain in the TLB.
3. INVALIDATE PAGE TABLE ENTRY cannot
be safely used to update a shared
location in main storage if the
possibility exists that another CPU or a channel may also be updating
the location. LOAD ADDRESS SPACE PARAMETERS
lASP [SSE] ,,- __ ' E_5_0 0_' _---'-'_B_t I I B, I o 16 20 32 36 47
The contents of the doubleword at the
first-operand location contain values to
be loaded into control registers 3 and
4, including a secondary ASN and a
primary ASN. Execution of the instruc­
tion consists in performing four major
steps: PASN translation, SASN trans­
lation, SASN authorization, and
control-register loading. Each of these
steps mayor may not be performed,
depending on the outcome of certain
tests and on the setting of bits 29-31
of the second-operand address. These steps, when successful, obtain addi­
tional values, which are loaded into