STORE-STATUS KEY Activating the store-status key initi­
ates a store-status operation. (See the
section "Store Status" in Chapter 4, "Control.") The store-status key is effective only
when the CPU is in the stopped state. Operation Note The store-status operation may be used
in conjunction with a standalone dump
program for the analysis of major
program malfunctions. For such an oper­
ation, the following sequence would be
called for:
1. Activation of the stop or system­
reset-normal key
2. Activation of the store-status key
3. Activation of the load-normal key
to enter a standalone dump program
The system-reset-normal key must be
activated in step 1 when (1) the stop
key is not effective because a contin­
uous string of interruptions is occur­
ring, (2) the prefix register contains
an invalid address, (3) a READ DIRECT instruction cannot be completed, or (4)
the CPU is in the check-stop state.
SYSTEM-RESET-CLEAR KEY Activating the system-reset-clear key
causes a clear-reset operation to be
performed. Clear reset is propagated to
all CPUs and storage units in the
configuration, and a subsystem reset is
performed on the remainder of the
configuration. For details, see the
section "Resets" in Chapter 4, "Control." The system-reset-clear key is effective
when the CPU is in the operating,
stopped, load, or check-stop state.
SYSTEM-RESET-NORMAl KEY When the store-status facility is not
installed, activating the system-reset­
normal key causes an initial-CPU-reset
operation and a subsystem-reset opera­
tion to be performed. When the store­
status facility is installed, activating
the system-reset-normal key causes a CPU-reset operation and a subsystem­
reset operation to be performed. In a
multiprocessing configuration, a CPU reset is propagated to all CPUs in the
configuration. For details, see the
section "Resets" in Chapter 4, "Control." The system-reset-normal key is effective
when the CPU is in the operating,
stopped, load, or check-stop state.
TEST INDICATOR The test indicator is on when a manual
control for operation or maintenance is
in an abnormal position that can affect
the normal operation of a program.
Setting the address-compare controls or
the check control to the stop position
or setting the rate control to the
instruction-step position turns on the
test indicator. Setting the interval­
timer control to the disable position
mayor may not turn on the test indica­
tor.
The test indicator may be on when one or
more diagnostic functions under the
control of DIAGNOSE are activated, or
when other abnormal conditions occur.
Operation Note
If a manual control is left in a setting
intended for maintenance purposes, such
an abnormal setting may, among other
things, result in false machine-check
indications or cause actual machine
malfunctions to be ignored. It may also
alter other aspects of machine
operation, including instruction
execution, channel operation, and the
functioning of operator controls and
indicators, to the extent that operation
of the machine does not comply with that
described in this publication.
The abnormal setting of a manual control
causes the test indicator of the
affected CPU to be turned oni however, in a multiprocessing configuration, the
operation of other CPUs may be affected
even though their test indicators are
not turned on. TOO-CLOCK CONTROL When the TOO-clock control is not acti­
vated, that is, the control is set to
the secure position, the state and value
of the TOO clock are protected against
unauthorized or inadvertent change by
not permitting the instructions SET CLOCK or DIAGNOSE to change the state or
value. Chapter 12. Operator Facilities 12-5

When the TOD-clock control is activated, that is, the control is set to the
enable-set position, alteration of the
clock state or value by means of SET CLOCK or DIAGNOSE is permitted. This
setting is momentary, and the control
automatically returns to the secure
position.
In a multiprocessing configuration,
activating the TOO-clock control enables
all TOO clocks in the configuration to
be set. If there is more than one phys­
ical representation of the TOO-clock control, no TOO clock is secure unless
all TOO-clock controls in the configura­
tion are set to the secure position.
WAIT INDICATOR The wait indicator is on when the wait­
state bit in the current PSW is one. MULTIPROCESSING CONFIGURATIONS In a multiprocessing configuration, one
of each of the following keys and
12-6 System/370 Principles of Operation
controls is provided for each CPU: alter and display, interrupt, rate, restart, start, stop, and store status.
The load-clear key, load-normal key, and
load-unit-address controls are provided
for each CPU capable of performing I/O operations. Alternatively, a single set
of initial-program-Ioading keys and
controls may be used together with a
control to select the desired CPU. There need not be more than one of each
of the following keys and controls in a multiprocessing configuration: address
compare, check, IML, interval timer, power, system reset clear, system reset normal, and TOO clock. One check-stop, manual, test, and wait
indicator is provided for each CPU. A
load indicator is provided only on a CPU capable of performing I/O operations.
Alternatively, a single set of indica­
tors may be switched to more than one CPU. In a system capable of reconfiguration,
there must be a separate set of keys,
controls, and indicators in each config­
uration.