accompanied by error indications from
the I/O device.
The indication of the conclusion of an I/O operation can be brought to the
attention of the program by an I/O interruption or, when the CPU is disa­
bled for I/O interruptions from the
channel, by programmed interrogation of
the I/O device. An indication that will
result in a request for an I/O inter­
ruption is called an interruption
condition. In either case, a CSW is
stored, which contains additional infor­
mation concerning the execution of the
operation. When channel end is indi­
cated in the CSW and no equipment
malfunctions have been detected, the CSW identifies the last CCW used and
provides its residual byte count, thus
indicating the extent of storage used.
Facilities are provided for the program
to initiate the execution of a chain of I/O operations with a single START I/O or START I/O FAST RELEASE instruction. When the chaining flags in the current CCW specify command chaining and no
unusual conditions have been detected in
the operation, the receipt of the
device-end signal causes the channel to
fetch a new CCW and, if the suspend flag
;s not specified in the new CCW, to
initiate execution of a new command at
the device. If the suspend flag is
specified, execution of the new command
is not initiated, and command chaining
is terminated. Execution of the new
command is initiated by the channel in
the same way as the previous operation. Channel end and device end are not
presented to the program when command
chaining causes execution of another I/O operation to be initiated. However,
unusual situations can cause premature
termination of command chaining and
generation of an I/O-interruption condi­
tion.
Activities that generate 1/0- interruption conditions are asynchronous
to activity in the CPU, and more than
one I/O-interruption condition can exist
at the same time. The channel and the CPU establish priority among the condi­
tions so that only one condition is
presented to the CPU at a time.
The execution of an I/O operation or
chain of I/O operations involves up to
four levels of participation:
1. Except for the effects caused by
the integration of CPU and channel
equipment, the CPU is busy for the
duration of execution of START I/O or START I/O FAST RELEASE, which
lasts at most until the addressed I/O device responds to the first
command.
2. The subchannel is busy with the
execution from the time condition
code 0 is set for the START I/O or
START I/O FAST RELEASE until the CPU has accepted the I/O inter­
ruption signaling that the I/O operation or, for chained oper­
ations, the last operation has been
completed at the subchannel.
3. The control unit may remain busy
after the execution has completed
at the subchannel and may generate
control-unit end when it becomes
free.
4. The I/O device is busy from the
initiation of the first operation
at the I/O device until the inter­
ruption condition caused by the
device end associated with the
operation is cleared from the I/O device.
An interruption condition caused by
device end blocks the initiation of an I/O operation with the I/O device, but
normally does not affect the state of
any other part of the system. An inter­
ruption condition caused by control-unit
end may block communications through the
control unit to any device attached to
it, and an interruption condition caused
by channel end normally blocks all
communications through the subchannel.
In some system models, a suspend-and­
resume facility may be provided on an
individual subchannel basis for
nonshared subchannels. The mechanism
for suspending channel-program execution
provides the program a controlling func­
tion over the execution of a channel
program. The initiation of the suspend
function is controlled by the setting of
the suspend-control bit in the CAW. The
suspend function is signaled to the
channel during channel-program execution
by a flag (that is, a bit set to one) in
the CCW. Suspension occurs when the channel
fetches a CCW with a valid S flag. The
command field of this CCW is not sent to
the I/O device, and the device is
signaled that the chain of commands is
terminated. A subsequent RESUME I/O (RIO) instruction informs the channel
that the suspend CCW may have been modi­
fied and that the channel must refetch
the CCW and examine the current settings
of the flags. If the suspend flag is
zero in the CCW, the channel resumes
execution of the chain of commands. COMPATIBILITY OF OPERATION The organization of the I/O system
provides for a uniform method of
controlling I/O operations. The capa­
bility of a channel, however, depends on
its use and on the CPU model to which it
is connected. Channels are provided
with different data-transfer capabili- Chapter 13. Input/Output Operations 13-7

ties, and an I/O device designed to
transfer data only at a specific rate (a
magnetic-tape unit or a disk storage,
for example) can operate only on a chan­
nel that can accommodate at least this
data rate.
The data rate a channel can accommodate
depends also on the way the I/O opera­
tion is programmed. The channel can
sustain its highest data rate when no
data chaining is specified. Oata chain­
ing reduces the maximum allowable rate,
and the extent of the reduction depends
on the frequency at which new CCWs are
fetched and on the address resolution of
the first byte in each new storage area.
Furthermore, since a channel shares
storage with the CPU and other channels,
activity in the rest of the system
affects the accessibility of storage
and, hence, the instantaneous load the
channel can sustain.
In view of the dependence of channel
capacity on programmlng and on activity
in the rest of the system, an evaluation
of the ability of elements in a specific I/O configuration to function concur­
rently must be based on a consideration
of both the data rate and the way the I/O operations are programmed. Two
systems differing in performance but
employing identical complements of I/O devices may be able to execute certain
programs in common, but it is possible
that other programs requiring, for exam­
ple, data chaining, may not run on one
of the systems because of the increased
load caused by the data chaining. CONTROL OF INPUT/OUTPUT DEVICES The CPU controls I/O operations by means
of 10 I/O instructions: CLEAR CHANNEL, CLEAR I/O, HALT DEVICE, HALT I/O, RESUME I/O, START I/O, START I/O FAST RELEASE, STORE CHANNEL 10, TEST CHANNEL, and TEST I/O. The instructions TEST CHANNEL, CLEAR CHANNEL, and STORE CHANNEL 10 address a
channel; they do not address an I/O device. The other seven I/O instructions address a channel and a
device on that channel. INPUT/OUTPUT DEVICE ADDRESSING
Within each channel set, an I/O device
and the associated access path are
designated by an I/O address. The
16-bit I/O address consists of two
parts: a channel address in the left­
most eight bit positions and a device
address in the rightmost eight bit posi­
tions.
13-8 System/370 Principles of Operation The channel address provides for identi­
fying up to 256 channels per channel
set. Channels are numbered 0-255. Channel 0 is a byte-multiplexer channel,
and each of channels 1-255 may be a
byte-multiplexer, block-multiplexer, or
selector channel.
The number and type of channels and
subchannels available, as well as their
address assignment, depend on the system
model and the particular installation.
The device address identifies the
particular I/O device and control unit
on the designated channel. The device
address identifies, for example, a
particular magnetic-tape drive, disk­
access mechanism, or transmission line.
Any number in the range 0-255 can be
used as a device address, providing
facilities for addressing up to 256
devices per channel. An exception is
some multiplexer channels that provide
fewer than the maximum configuration of
subchannels and hence do not permit use
of the corresponding unassignable device
addresses.
Devices that do not share a control unit
with other devices may be assigned any
device address in the range 0-255, provided the device address is not
recognized by any other control unit.
Logically, such devices are not distin­
guishable from their control unit, and
both are identified by the same device
address.
Devices sharing a control unit (for
example, magnetic-tape drives or disk­
access mechanisms) are assigned device
addresses within sets of contiguous
numbers. The size of such a set is
equal to the maximum number of devices
that can share the control unit, or 16,
whichever is smaller. Furthermore, such
a set starts with a device address in
which the number of rightmost zeros is
at least equal to the number of bit
positions required for specifying the
set size. The leftmost bit positions of
a device address within such a set iden­
tify the control unit, and the rightmost
bit positions designate the device on
the control unit. Control units designed to accommodate
more than 16 devices may be assigned
nonsequential sets of device addresses,
each set consisting of 16, or the number required to bring the total number of
assigned device addresses equal to the
maximum number of devices attachable to
the control unit, whichever is smaller.
The device-addressing facilities are
added in increments of a set so that the
number of device addresses assigned to a
control unit does not exceed the number
of devices attached by more than 15.
The control unit does not respond to any
device address outside its assigned set
or sets. For example, if a control unit