This pUblication provides, for reference
purposes, a detailed definition of the
machine functions performed bySystem/370. The publication applies only to systems
operating in theSystem/370 mode. The
IBM370-XA Principles of Operation, SA22-7085, should be consulted regarding
the functions of the architecture which
apply to systems operating in the370-XA mode, and the IBM 4300 Processors Prin
ciples ofOperation for ECPS:VSE Mode, GA22-7070, should be consulted regarding
the functions of the architecture which
apply only to systems operating in the
VSE mode.
The publication describes each function
at the level of detail needed to prepare
an assembler-language program that
relies on that function. It does not,
however, describe the notation and
conventions that must be employed in
preparing sucha program, for which the
user must instead refer to the appropri
ate assembler-language publication.
The information in this publication is
provided principally for use by
assembler-language programmers, although
anyone concerned with the functional
details ofSystem/370 will find it
useful.
This publication is written as a refer
ence and should not be considered an
introduction or a textbook. It assumes
the user has a basic knowledge of data
processing systems. IBM publications
relating toSystem/370 are listed and
described in the IBMSystem/370, 30xx, and 4300 Processors Bibliography, GC20-0001. All facilities discussed in this publi
cation are not necessarily available on
every model. Furthermore, in some
instances the definitions have been
structured to allow for some degree of
extendibility, and therefore certain
capabilities may be described or implied
that are not offered on any model.
Examples of such capabilities are the
number of channel-mask bits in the
control register, the size of the CPU
address, and the number ofCPUs sharing
main storage. The allowance for this
type of extendibility should not be
construed as implying any intention by
IBM to provide such capabilities. For
information about the characteristics
and availability of facilities on a
specific model, see the functional char
acteristics publication for that model. Largely because this publication is arranged for reference, certain words ; PREFACE and phrases appear, of necessity, earli
er in the publication than the principal
discussions explaining them. The reader
who encountersa problem because of this
arrangement should refer to the index,
which indicates the location of the key
description.
The information presented in this publi
cation is grouped in 13 chapters and
several appendixes:
Chapter 1, Introduction, highlights some
of the major facilities ofSystem/370. Organization, describes the
major groupings within the system --the
central processing unit(CPU), storage,
and input/output --with some attention
given to the composition and character
istics of those groupings.Chapter d, Storage, explains the infor
mation formats, the addressing of stor
age, and the facilities for storage
protection. It also deals with dynamic
address translation (OAT), which,
coupled with special programming
support, makes the use of a virtual
storage possible inSystem/370. Dynamic
address translation eliminates the need
to assign a program to a fixed in real storage and thus reduces the
addressing constraints on system and
problem programs.Chapter Control, describes the facil
ities for the switching of system
status, for special externally initiated
operations, for debugging, and for
timing. It deals specifically withCPU states, control modes, the program
status word (PSW), control registers,
program-event recording, timing facili
ties, resets, store status, and initial
program loading.Chapter 2, Program Execution, explains
the role of instructions in program
execution, looks in detail at instruc
tion formats, and describes briefly the
use of the program-status word (PSW), of
branching, and of interruptions. It
contains the principal description of
the dual-address-space (DAS) facility.
It also details the aspects of program
execution on oneCPU as observed by
otherCPUs and by channels. Chapter Interruptions, details the
mechanism that permits theCPU to change
its state as a result of conditions
external to the system, within the
system, or within theCPU itself. Six
classes of interruptions are identified
and described: machine-check interrup
tions, program interruptions, super
visor-call interruptions, external
iii
purposes, a detailed definition of the
machine functions performed by
operating in the
IBM
the functions of the architecture which
apply to systems operating in the
ciples of
the functions of the architecture which
apply only to systems operating in the
VSE mode.
The publication describes each function
at the level of detail needed to prepare
an assembler-language program that
relies on that function. It does not,
however, describe the notation and
conventions that must be employed in
preparing such
user must instead refer to the appropri
ate assembler-language publication.
The information in this publication is
provided principally for use by
assembler-language programmers, although
anyone concerned with the functional
details of
useful.
This publication is written as a refer
ence and should not be considered an
introduction or a textbook. It assumes
the user has a basic knowledge of data
processing systems. IBM publications
relating to
described in the IBM
cation are not necessarily available on
every model. Furthermore, in some
instances the definitions have been
structured to allow for some degree of
extendibility, and therefore certain
capabilities may be described or implied
that are not offered on any model.
Examples of such capabilities are the
number of channel-mask bits in the
control register, the size of the CPU
address, and the number of
main storage. The allowance for this
type of extendibility should not be
construed as implying any intention by
IBM to provide such capabilities. For
information about the characteristics
and availability of facilities on a
specific model, see the functional char
acteristics publication for that model.
er in the publication than the principal
discussions explaining them. The reader
who encounters
arrangement should refer to the index,
which indicates the location of the key
description.
The information presented in this publi
cation is grouped in 13 chapters and
several appendixes:
Chapter 1, Introduction, highlights some
of the major facilities of
major groupings within the system --the
central processing unit
and input/output --with some attention
given to the composition and character
istics of those groupings.
mation formats, the addressing of stor
age, and the facilities for storage
protection. It also deals with dynamic
address translation (OAT), which,
coupled with special programming
support, makes the use of a virtual
storage possible in
address translation eliminates the need
to assign a program to a fixed
addressing constraints on system and
problem programs.
ities for the switching of system
status, for special externally initiated
operations, for debugging, and for
timing. It deals specifically with
status word (PSW), control registers,
program-event recording, timing facili
ties, resets, store status, and initial
program loading.
the role of instructions in program
execution, looks in detail at instruc
tion formats, and describes briefly the
use of the program-status word (PSW), of
branching, and of interruptions. It
contains the principal description of
the dual-address-space (DAS) facility.
It also details the aspects of program
execution on one
other
mechanism that permits the
its state as a result of conditions
external to the system, within the
system, or within the
classes of interruptions are identified
and described: machine-check interrup
tions, program interruptions, super
visor-call interruptions, external
iii