R t Address
(even)1////////1 First-Operand 0 8 31
R
t +1 First-Operand Length
(odd)1////////1 1 0 8 31
R2
(even)1////////1 Second-Operand Addressl 0 8 31
R 2 +1Ipad By tel Second-Operand Length I (odd)" .
o 8 31
Since theCLCL instruction may be inter
rupted during execution, the interrupt
ing program must preserve the contents
of the four registers for use when the
instruction is resumed.
The following instructions set up two
register pairs to control a text-string
comparison. For example, assume:
Operand! Address: 20800{16} Length: 100{10} Operand Address: 20AOO{16} Length: 132{10} Padding Byte
Address:20003{16} Length: 1
Value:40{16} Register 12 contains 00 02 00 00. The setup instructions are:
LA4,X'800'(12) Set register 4 to
start of first
operand
LA5,100 Set register 5 to
length of first
operand
LA8,X'AOO'(12) Set register 8 to
start of second
operand
LA 9,132Set register 9 to
length of second
operandICM 9,B'1000',3(12) Insert padding byte
in leftmost byte
position of regis-
ter 9
Register pair 4,5 defines the first
operand. Bits 8-31 of register 4
contain the storage address of the start
of anEBCDIC text string, and bits 8-31
of register 5 contain the length of the
string, in this case100 bytes.
Register pair 8,9 defines the second
operand, with bits 8-31 of register 8
containing the starting location of the
second operand and bits 8-31 of register
9 containing the length of the second
operand, in this case 132 bytes. Bits0-7 of register 9 contain an EBCDIC blank character (X'40') to pad the
shorter operand. In this example, the
padding byte is used in the first oper
and, after the100th byte, to compare
with the remaining bytes in the second
operand.
With the register pairs thus set up, the
format of theCLCL instruction is:
Machine FormatOp Code OF 4 8
Assembler FormatCLCL 4,8
When this instruction is executed, the
comparison starts at the left end of
each operand and proceeds to the right.
The operation ends as soon as an
inequality is detected or the end of the
longer operand is reached.
If thisCLCL instruction is interrupted
after60 bytes have compared equal, the
operand lengths in registers 5 and 9
will have been decremented to40 and 72,
respectively. The operand addresses in
registers 4 and 8 will have been incre
mented toX'2083C' and X'20A3C'j the
leftmost byte of registers 4 and 8 will
have been set to zero. The padding byteX'40' remains in register 9. When the ClCl instruction is reexecuted with these register contents, the comparison
resumes at the point of interruption.
Now, assume that the instruction is
interrupted after110 bytes. That is,
the first100 bytes of the second oper
and have compared equal to the first
operand, and the next10 bytes of the
second operand have compared equal to
the padding byte (blank). The residual
operand lengths in registers 5 and 9 are
o and 22, respectively, and the operand
addresses in registers 4 and 8 areX'20864' (the value when the first oper
and was exhausted) andX'20A6E' (the
current value for the second operand).
When the comparison ends, the condition
code is set to0, I, or 2, depending on
whether the first operand is equal to,
less than, or greater than the second
operand, respectively.
Appendix A. Number Representation and Instruction-Use Examples A-15
(even)
R
t +1 First-Operand Length
(odd)
R2
(even)
R 2 +1
o 8 31
Since the
rupted during execution, the interrupt
ing program must preserve the contents
of the four registers for use when the
instruction is resumed.
The following instructions set up two
register pairs to control a text-string
comparison. For example, assume:
Operand
Address:
Value:
LA
start of first
operand
LA
length of first
operand
LA
start of second
operand
LA 9,132
length of second
operand
in leftmost byte
position of regis-
ter 9
Register pair 4,5 defines the first
operand. Bits 8-31 of register 4
contain the storage address of the start
of an
of register 5 contain the length of the
string, in this case
Register pair 8,9 defines the second
operand, with bits 8-31 of register 8
containing the starting location of the
second operand and bits 8-31 of register
9 containing the length of the second
operand, in this case 132 bytes. Bits
shorter operand. In this example, the
padding byte is used in the first oper
and, after the
with the remaining bytes in the second
operand.
With the register pairs thus set up, the
format of the
Machine Format
Assembler Format
When this instruction is executed, the
comparison starts at the left end of
each operand and proceeds to the right.
The operation ends as soon as an
inequality is detected or the end of the
longer operand is reached.
If this
after
operand lengths in registers 5 and 9
will have been decremented to
respectively. The operand addresses in
registers 4 and 8 will have been incre
mented to
leftmost byte of registers 4 and 8 will
have been set to zero. The padding byte
resumes at the point of interruption.
Now, assume that the instruction is
interrupted after
the first
and have compared equal to the first
operand, and the next
second operand have compared equal to
the padding byte (blank). The residual
operand lengths in registers 5 and 9 are
o and 22, respectively, and the operand
addresses in registers 4 and 8 are
and was exhausted) and
current value for the second operand).
When the comparison ends, the condition
code is set to
whether the first operand is equal to,
less than, or greater than the second
operand, respectively.
Appendix A. Number Representation and Instruction-Use Examples A-15