R t Address
(even) 1////////1 First-Operand 0 8 31
R
t +1 First-Operand Length
(odd) 1////////1 1 0 8 31
R2
(even) 1////////1 Second-Operand Addressl 0 8 31
R 2 +1 Ipad By tel Second-Operand Length I (odd)" .
o 8 31
Since the CLCL instruction may be inter­
rupted during execution, the interrupt­
ing program must preserve the contents
of the four registers for use when the
instruction is resumed.
The following instructions set up two
register pairs to control a text-string
comparison. For example, assume:
Operand ! Address: 20800{16} Length: 100{10} Operand Address: 20AOO{16} Length: 132{10} Padding Byte
Address: 20003{16} Length: 1
Value: 40{16} Register 12 contains 00 02 00 00. The setup instructions are:
LA 4,X'800'(12) Set register 4 to
start of first
operand
LA 5,100 Set register 5 to
length of first
operand
LA 8,X'AOO'(12) Set register 8 to
start of second
operand
LA 9,132 Set register 9 to
length of second
operand ICM 9,B'1000',3(12) Insert padding byte
in leftmost byte
position of regis-
ter 9
Register pair 4,5 defines the first
operand. Bits 8-31 of register 4
contain the storage address of the start
of an EBCDIC text string, and bits 8-31
of register 5 contain the length of the
string, in this case 100 bytes.
Register pair 8,9 defines the second
operand, with bits 8-31 of register 8
containing the starting location of the
second operand and bits 8-31 of register
9 containing the length of the second
operand, in this case 132 bytes. Bits 0-7 of register 9 contain an EBCDIC blank character (X'40') to pad the
shorter operand. In this example, the
padding byte is used in the first oper­
and, after the 100th byte, to compare
with the remaining bytes in the second
operand.
With the register pairs thus set up, the
format of the CLCL instruction is:
Machine Format Op Code OF 4 8
Assembler Format CLCL 4,8
When this instruction is executed, the
comparison starts at the left end of
each operand and proceeds to the right.
The operation ends as soon as an
inequality is detected or the end of the
longer operand is reached.
If this CLCL instruction is interrupted
after 60 bytes have compared equal, the
operand lengths in registers 5 and 9
will have been decremented to 40 and 72,
respectively. The operand addresses in
registers 4 and 8 will have been incre­
mented to X'2083C' and X'20A3C'j the
leftmost byte of registers 4 and 8 will
have been set to zero. The padding byte X'40' remains in register 9. When the ClCl instruction is reexecuted with these register contents, the comparison
resumes at the point of interruption.
Now, assume that the instruction is
interrupted after 110 bytes. That is,
the first 100 bytes of the second oper­
and have compared equal to the first
operand, and the next 10 bytes of the
second operand have compared equal to
the padding byte (blank). The residual
operand lengths in registers 5 and 9 are
o and 22, respectively, and the operand
addresses in registers 4 and 8 are X'20864' (the value when the first oper­
and was exhausted) and X'20A6E' (the
current value for the second operand).
When the comparison ends, the condition
code is set to 0, I, or 2, depending on
whether the first operand is equal to,
less than, or greater than the second
operand, respectively.
Appendix A. Number Representation and Instruction-Use Examples A-15

When the operands are unequal, the
addresses in registers 4 and 8 indicate
the bytes that caused the mismatch. CONVERT TO BINARY (CVB) The CONVERT TO BINARY instruction
converts an eight-byte, packed-decimal
number into a signed binary integer and
loads the result into a general
register. After the conversion opera­
tion is completed, the number is in the
proper form for use as an operand in
signed binary arithmetic. For example,
assume:
Storage locations 7608-760F contain a
decimal number in the packed
format: 00 00 00 00 00 25 59 4C (+25,594).
The contents of register 7 are not
significant.
Register 13 contains 00 00 76 00. The format of the conversion instruction
is:
Machine Format Op Code 4F 7 o D 008
1 Assembler Format Op Code R
t ,D
2
(X
2
,B
2
) CVB 7,8(0,13) After the instruction is executed,
register 7 contains 00 00 63 FA. CONVERT TO DECIMAL (CVD) The CONVERT TO DECIMAL instruction is
the opposite of the CONVERT TO BINARY instruction. CVD converts a signed
binary integer in a register to packed
decimal and stores the eight-byte
result. For example, assume:
Register 1 contains the signed binary
integer: 00 00 OF OF. Register 13 contains 00 00 76 00. The format of the instruction is:
A-16 System/370 Principles of Operation
Machine Format Op Code R t
4E 1 o D 008
1 Assembler Format CVD 1,8(0,13) After the instruction is executed, stor­
age locations 7608-760F contain 00 00 00 00 00 03 85 5C (+3855).
The plus sign generated is the preferred
plus sign, 1100{2}. DIVIDE (D, DR)
The DIVIDE instruction divides the divi­
dend in an even-odd register pair by the
divisor in a register or in storage. Since the instruction assumes the divi­
dend to be 64 bits long, it is important
first to extend a 32-bit dividend on the
left with bits equal to the sign bit.
For example, assume that:
Storage locations 3550-3553 contain 00 00 08 DE = 2270{10} (the
dividend).
Storage locations 3554-3557 contain 00 00 00 32 = 50{10} (the divisor).
The initial contents of registers 6 and
7 are not significant.
Register 8 contains 00 00 35 50. The following assembler-language state­
ments load the registers properly and
perform the divide operation:
Statement Comments L 6,0(0,8) Places 00 00 08 DE into
register 6 .
SRDA 6,32(0) Shifts 00 00 08 DE into
register 7 . Register
6 i s filled with zeros
(sign bits).
D 6,4(0,8) Performs the division.
The machine format of the above DIVIDE instruction is:
Machine Format Op Code R t X 2 B2 D2 5D 6 0 8 004
1