The following figures list instructions
by name, mnemonic, operation code, and
facility. Some models may offer
instructions that do not appearin the
figures, such as those provided for
assists or as part of special or custom
features.
The operation codes for the vectorfacility are not included in this appen
dix. See the pUblication IBM System/370
Vector Operations, SA22-7125, for opera
tion codes associated withthis facility.
The operation code00 hex with a
two-byte instruction format is allocated
for use by the program when an indi
cation of an invalid operation is
required. Itis improbable that this
operation code will ever be assigned to
an instruction implemented in theCPU. Explanation of Symbols in "Character istics" and Code" Columns 9 Causes serialization and checkpoint
synchronization.9
1 Causes serialization and checkpoint
synchronization when the Mt andR2 fields contain all ones and all
zeros, respectively.
$ Causes serialization.* The handling of bits 8-15 of the
operation code for some of the I/O
instructions depends on the
instruction and thefacilities installed. See the description of
the instruction for details.
A Access exceptions for logical
addresses.
Al Access exceptions; not all access
exceptions may occur; see instruction description for details.
AI Access exceptions for instruction
address.
AS Access exceptions and ASN
translation-specification
exception; see instruction descrip
tion for details.
AT ASN-translation exceptions (which
include addressing, ASN-translation
specification, AFX translation, and
ASX translation>.
BPER branch event.
BS Branch-and-save facility.
C Condition code is set.
CKCPU-timer and clock-comparator
facility.
CS Channel-set-switching facility.
D Data exception.
DC Direct-control facility.
DF Decimal-overflow exception.
DK Decimal-divide exception.
DM Depending on the model, DIAGNOSE
may generate various program
exceptions and may change the
condition code.
DU Dual-address-space facility.
EF Extended facility.
EK
EO
EU
EX
FKFP GO Gl
G2
GM
IF
II
IK
L
LS
MI
MOMP P PK Q
R
RE
RR
RRE
RS
RX
S
SD
SISO SP SR
SS
SSE
ST
SW
T
TB
TRXP APPENDIX LISTS OF INSTRUCTIONS
Storage-key-instruction-extension
facility.
Exponent-overflow exception.
Exponent-underflow exception.
Execute exception.
Floating-point-divide exception.
Floating-point facility.
Instruction execution includes the
implied use of general registerO. Instruction execution includes the
implied use of general registerI. Instruction execution includes the
implied use of general register 2.
Instruction execution includes the
implied use of multiple general
registers.
Fixed-point-overflow exception.
Interruptible instruction.
Fixed-point-divide exception.
New condition code is loaded.
Significance exception.
Move-inverse facility.
Monitor event.
Multiprocessing facility.
Privileged-operation exception.
PSW-key-handling facility.
Privileged-operation exception for
semiprivileged instructions.PER general-register-alteration
event.
Recovery-extension facility.
RR instruction format.
RRE instruction format.
RS instruction format.
RX instruction format.
S instruction format.PER storage-alteration event, which
can be caused by READ DIRECT only
when INVALIDATEPAGE TABLE ENTRY is
not installed.
SI instruction format.
Special-operation exception.
Specification exception.
Suspend-and-resume facility.
SS instruction format.
SSE instruction format.PER storage-alteration event.
Conditional-swapping facility.
Trace exceptions (which include
access and specification).
Test-block facility.
Translation facility.
Extended-precision floating-point
facility.
Additional exceptions and events
forPROGRAM CALL (which include
addressing, EX translation, LX
translation, PC-translation speci
fication, and special-operation
exceptions and space-switch event).
Additional exceptions and events
forPROGRAM TRANSFER (which include
addressing, primary authority, and
special-operation exceptions and
space-switch event).
Additional exceptions for SET
SECONDARY ASN (which include ad
dressing, secondary authority, and
special operation).
Appendix B. Lists of Instructions B-1
by name, mnemonic, operation code, and
facility. Some models may offer
instructions that do not appear
figures, such as those provided for
assists or as part of special or custom
features.
The operation codes for the vector
dix. See the pUblication IBM System/370
Vector Operations, SA22-7125, for opera
tion codes associated with
The operation code
two-byte instruction format is allocated
for use by the program when an indi
cation of an invalid operation is
required. It
operation code will ever be assigned to
an instruction implemented in the
synchronization.
1
synchronization when the Mt and
zeros, respectively.
$ Causes serialization.
operation code for some of the I/O
instructions depends on the
instruction and the
the instruction for details.
A Access exceptions for logical
addresses.
Al Access exceptions; not all access
exceptions may occur; see instruc
AI Access exceptions for instruction
address.
AS Access exceptions and ASN
translation-specification
exception; see instruction descrip
tion for details.
AT ASN-translation exceptions (which
include addressing, ASN-translation
specification, AFX translation, and
ASX translation>.
B
BS Branch-and-save facility.
C Condition code is set.
CK
facility.
CS Channel-set-switching facility.
D Data exception.
DC Direct-control facility.
DF Decimal-overflow exception.
DK Decimal-divide exception.
DM Depending on the model, DIAGNOSE
may generate various program
exceptions and may change the
condition code.
DU Dual-address-space facility.
EF Extended facility.
EK
EO
EU
EX
FK
G2
GM
IF
II
IK
L
LS
MI
MO
R
RE
RR
RRE
RS
RX
S
SD
SI
SS
SSE
ST
SW
T
TB
TR
Storage-key-instruction-extension
facility.
Exponent-overflow exception.
Exponent-underflow exception.
Execute exception.
Floating-point-divide exception.
Floating-point facility.
Instruction execution includes the
implied use of general register
implied use of general register
implied use of general register 2.
Instruction execution includes the
implied use of multiple general
registers.
Fixed-point-overflow exception.
Interruptible instruction.
Fixed-point-divide exception.
New condition code is loaded.
Significance exception.
Move-inverse facility.
Monitor event.
Multiprocessing facility.
Privileged-operation exception.
PSW-key-handling facility.
Privileged-operation exception for
semiprivileged instructions.
event.
Recovery-extension facility.
RR instruction format.
RRE instruction format.
RS instruction format.
RX instruction format.
S instruction format.
can be caused by READ DIRECT only
when INVALIDATE
not installed.
SI instruction format.
Special-operation exception.
Specification exception.
Suspend-and-resume facility.
SS instruction format.
SSE instruction format.
Conditional-swapping facility.
Trace exceptions (which include
access and specification).
Test-block facility.
Translation facility.
Extended-precision floating-point
facility.
Additional exceptions and events
for
addressing, EX translation, LX
translation, PC-translation speci
fication, and special-operation
exceptions and space-switch event).
Additional exceptions and events
for
addressing, primary authority, and
special-operation exceptions and
space-switch event).
Additional exceptions for SET
SECONDARY ASN (which include ad
dressing, secondary authority, and
special operation).
Appendix B. Lists of Instructions B-1