APPENDIX CHANGES AFFECTING COMPATIBILITY WITHIN SYSTEM/370 READ DIRECT and WRITE DIRECT •••••.••...•••.•...•.••.••.. 1-1
Store Accesses ..•.........•...•.•.••.................... 1-1
Fetch Accesses ..•.........••••..••••...•••..•.....•..... 1-1 Operand-Access Consistency •••.......••.•..•..•••••.•.... 1-2 Change Bit ........................•..••.•......•••.••... 1-2
Subchannel Interruption-Pending state ...•............... 1-2
START I/O and START I/O FAST RELEASE .................... 1-2
This appendix summarizes those changes
included in the System/370 architecture
that may affect whether or not a program
written according to the original System/370 architecture will operate on
models implementing the architecture
described in this publication. Not included here are descriptions of
compatible extensions, such as new
facilities incorporated in System/370 that make use of unassigned operation
codes and formats.
READ DIRECT AND WRITE DIRECT When the instruction INVALIDATE PAGE TABLE ENTRY is installed, the following
changes apply:
• Both READ DIRECT and WRITE DIRECT are changed to use real instead of
logical addresses.
• Program-event recording does not
apply to the storage alteration
performed by READ DIRECT. STORE ACCESSES The following changes are made as to
when an access to storage for storing
can take place.
• When the execution of the instruc­
tion is nullified or suppressed because of certain program
exceptions, an interlocked-update
reference may occur at the operand
location. Originally no storage
access was permitted. In some of
these situations, the channel may
observe intermediate results which
differ from the final result. See the section "Exceptions to Nullifi­ cation and Suppression" in Chapter
5, "Program Execution." • • • When the mask in STORE CHARACTERS UNDER MASK i s zero, an interlocked-update reference may
occur at the byte location desig­
nated by the operand address. Originally no storage access was
permitted.
When the result of comparison in COMPARE AND SWAP or COMPARE DOUBLE AND SWAP is unequal, an
interlocked-update reference may
occur at the operand location.
Originally no storage access was
permitted.
When the result of the store opera­
tion is defined to be
unpredictable, such as for STORE CLOCK with the clock in the error
state, the store access may be
omitted.
Whether or not a store access takes
place is visible to the program in four
ways: an access exception may be indi­ cated, the change bit may be set, a PER storage-alteration event may be indi­
cated, and, for stores that are part of
an interlocked-update reference, the
channel may observe the distinct
accesses for fetching and storing. The
fetch and store parts of an
interlocked-update reference appear
interlocked to other CPUs. FETCH ACCESSES Originally the definition required that,
with the exception of some compare
instructions, access exceptions on
fetching be indicated for the unused
portion of an operand. The changed
definition permits the indication of the
access exception for the unused parts to
be unpredictable, except that an access
exception still must be indicated for
TEST UNDER MASK, INSERT CHARACTERS UNDER MASK, and COMPARE LOGICAL CHARACTERS UNDER MASK when the mask is zero.
Changes Affecting Compatibility within System/370 I-I

OPERAND-ACCESS CONSISTENCY Originally the access for the operand of LOAD MULTIPLE was specified to be doubleword-concurrenti that is, all
bytes within a doubleword appear to all
CPUs to be accessed concurrently. This
definition is changed to require double­
word concurrency only if the operand is
designated on a word boundary.
The restriction is removed that, during
the padding portion of a MOVE LONG execution, another CPU can observe the
operand to be stored only once and only
in the left-to-right sequence. CHANGE BIT Originally the System/370 architecture
specified that the change bit be set to
one each time information is stored in
the corresponding storage block. This
definition is changed as follows: • The change bit now is necessarily
set to one only when the contents
of the corresponding storage block
are changed. In situations where
execution of the instruction can be
completed without making a store
access, such as in MOVE (MVC) with
coincident operands or in OR (01) with an immediate operand of zeros, the change bit may be unaffected.
However, even when the change bit
is not set, any applicable access
exceptions or PER storage- alteration events are still
indicated. • The change bit may be set to one as a result of those situations
described in the section "Store Accesses" in this appendix. • Because of CPU retry, the change
bit may be set to one for locations
which the program has not accessed. SUBCHANNEL INTERRUPTION-PENDING STATE Originally only status associated with
the termination of an 110 operation at
1-2 System/370 Principles of Operation the subchannel could cause the subchan­
nel to enter the interruption-pending
state. Status not associated with the
termination of an I/O operation at the
subchannel was held pending at the
device, and the subchannel would be available. The changed definition
allows status not associated with the
termination of an I/O operation at the
subchannel to be accepted into the
subchannel. As a result of this change, a subchannel that is shared among multi­ ple devices may cause condition code 2
to be returned to a START I/O, START I/O FAST RELEASE, or TEST 110 even if no
previous START I/O or START I/O FAST RELEASE had been executed specifying the
same device. This busy state persists
until the interruption condition is
cleared. START I/O AND START I/O FAST RELEASE Originally the System/370 architecture
specified START 110 and START I/O FAST RELEASE as having the operation codes 9COO and 9C01, respectively, with bits
8-14 of the operation code ignored by
the CPU. Now, however, when the
suspend-and-resume facility is
installed, bits 8-14 of the operation
code for START I/O and START I/O FAST RELEASE are longer ignored by the CPU. Operation codes 9CXO, 9CX2, 9CX4, 9CX6, 9CX8, 9CXA, 9CXC, and 9CXE (wi th X
representing any hex digit) all were
executed as START I/O. Similarly, oper­
ation codes 9CX1, 9CX3, 9CX5, 9CX7, 9CX9, 9CXB, 9CXD, and 9CXF all were
executed as START I/O FAST RELEASE. When the suspend-and-resume facility is installed, only operation code 9COO is executed as START I/O, and only opera­
tion code 9COl is executed as START I/O FAST RELEASE; operation code 9C02 is executed as RESUME I/O, and all opera­ tion codes in the range 9C03 through 9CFF cause an operation exception to be
recognized.