Page-Table Lookup
The page-index portion of the virtual
address, in conjunction with the page­
table origin contained in the segment­
table entry, is used to select an entry
from the page table.
The 24-bit real address of the page­
table entry is obtained by appending
three zeros to the right of bits 8-28 of
the segment-table entry and adding the
page index, with the rightmost bit posi­
tion of the page index aligned with bit 30 of the address. A carry, if any,
into bit position 7 is ignored. With
extended real addressing, this 24-bit
real address is extended on the left
with zeros; thus, the page table can
wrap from 224 - 1 to zero.
As part of the page-table-Iookup
process, the four leftmost bits of the page index are compared against the
page-table length, bits 0-3 of the
segment-table entry, to establish wheth­ er the addressed entry is within the
table. If the value in the page-table­
length field is less than the value in
the four leftmost bit positions of the
page-index field, a page-translation
exception is recognized.
The two bytes of the page-table entry
appear to be fetched concurrently as
observed by other CPUs. The fetch
access is not subject to protection.
When the storage address generated for
fetching the page-table entry designates
a location which is not available in the
configuration, an addressing exception
is recognized, and the unit of operation
is suppressed.
The entry fetched from the page table
indicates the availability of the page
and contains the leftmost bits of the
page-frame real address. The page­
invalid bit is inspected to establish
whether the corresponding page is avail­
able. If this bit is one, a page­
translation exception is recognized. If
bit positions 13-14 for 4K-byte pages or
bit position 14 for 2K-byte pages
contains a one, a translation­
specification exception is recognized.
When the extended-real-addressing facil­
ity is installed, bit positions 13 and
14 of the page-table entry for 4K-byte
pages are used as bits 6 and 7 of the
page-frame real address and do not cause
a translation-specification exception
when either bit is one.
Formation of the Real Address When no exceptions in the translation
process are encountered, the page-frame
real address obtained from the page­
table entry and the byte-index portion
of the virtual address are concatenated,
with the page-frame real address forming
the leftmost part. The result is the
real storage address which corresponds
to the virtual address.
Recognition of Exceptions during Trans­
lation
Invalid addresses and invalid formats
can cause exceptions to be recognized
during the translation process.
Exceptions are recognized when informa­
tion contained in control registers or
table entries is used for translation
and is found to be incorrect.
The information pertaining to OAT is
considered to be used when an instruc­
tion is executed with DAT on or when
INVALIDATE PAGE TABLE ENTRY or LOAD REAL
ADDRESS ;s executed. The information is not considered to be used when the PSW specifies OAT on but an I/O, external,
restart, or machine-check interruption
occurs before an instruction is executed, or when the PSW specifies the
wait state. Only that information
required in order to translate a virtual
address is considered to be in use
during the translation of that address,
and, in particular, addressing
exceptions that would be caused by the
use of the PSTD or the SSTD are not
recognized when the translation of an
address uses only the SSTD or only the PSTD, respectively.
A list of translation exceptions, with
the action taken for each exception and
the priority in which the exceptions are recognized when more than one is appli­
cable, is provided in the section
"Recognition of Access Exceptions" in Chapter 6, "Interruptions." TRANSLATION-LOOKASIDE BUFFER
To enhance performance, the dynamic­
address-translation mechanism normally
is implemented such that some of the
information specified in the segment and
page tables is maintained in a special
buffer, referred to as the translation­
lookaside buffer (TLB). The CPU neces­
sarily refers to a OAT-table entry in
real storage only for the initial access
to that entry. This information may be
placed in the TLB, and subsequent trans­
lations may be performed by using the
information in the TLB. The presence of
the TLB affects the translation process
to the extent that a modification of the
contents of a table entry in real stor­
age does not necessarily have an Chapter 3. Storage 3-31

immediate effect, if any, on the trans­
lation.
The size and the structure of the TLB
depend on the model. For instance, the
TLB may be implemented in such a way as
to contain only a few entries pertaining
to the currently designated segment
table, each entry consisting of the
leftmost portion of a virtual address
and its corresponding page-frame real
address and segment-protection bit; or
it may contain arrays of values where
the page-frame real address and segment-protection bit are selected on
the basis of the effective segment-table
origin, the translation format, and the
leftmost bits of the virtual address.
Entries within the TLB are not explicit­
ly addressable by the program. In a multiple-CPU configuration, each CPU has its own TLB.
The description of the logical structure
of the TLB covers all implementations by System/370 models. The TLB entries are
considered as being of two types: TLB
segment-table entries and TLB page-table
entries. A TLB entry is considered as containing within it both the informa­
tion obtained from the table entry in real storage and the attributes used to
fetch the entry from storage. Thus, a TLB segment-table entry would contain
the following fields: I TF ISTO I SX IPTO IPTl C P TF The translation format in effect when the entry was formed STO The segment-table origin in effect
when the entry was formed
SX The segment index used to select
the entry PTO The page-table origin fetched from
the segment-table entry in real storage PTL The page-table length fetched from
the segment-table entry in real
storage
C The common-segment bit fetched
from the segment-table entry in real storage; when the common­
segment facility is not installed,
this field is not included in the
TlB P The segment-protection bit fetched
from the segment-table
real storage; when the
protection facility installed, this field included in the TlB.
entry in
segment-
is not
is not
A TLB page-table entry would contain the
following fields:
3-32 System/370 Principles of Operation
TF IPTO PX IPFRAI TF The translation format in effect
when the entry was formed PTO The page-table origin in effect
when the entry was formed PX The page index used to select the
entry PFRA The page-frame real address
fetched from the page-table entry
in real storage. When the
extended-real-addressing facility
is installed, this field for
4K-byte pages includes the
extended-storage-address bits.
Depending on the implementation, not all of the above items are required in the
TlB. For example, if the implementation
combines into a single TlB entry (1) the
information obtained from a page-table
entry and (2) the attributes of both the
page-table entry and the segment-table
entry, then the page-table-origin and
page-table-length fields are not
required.
Note: The following sections describe
the conditions under which information
may be placed in the TLB and information
from the TLB may be used for address
translation, and they describe how changes to the translation tables affect
the translation process. Information is
not necessarily retained in the TlB
under all conditions for which such
retention is permissible. Furthermore,
information in the TlB may be cleared
under conditions additional to those for
which clearing is mandatory.
Use of the Translation-lookaside Buffer
The formation of TlB entries and the
effect of any manipulation of the
contents of a table entry in real stor­
age by the program depend on whether the
entry is valid, on whether the entry is
attached to a particular CPU, on whether
a copy of the entry can be placed in the
TLB of a particular CPU, and on whether
a copy in the TlB of the entry is
usable.
The valid state of a table entry denotes or page associated with
the table entry is available. An entry
is valid when the segment-invalid bit or page-invalid bit in the entry is zero. The attached state of a table entry
denotes that the CPU to which it is attached can attempt to use the table
entry for implicit address translation.
The table entry may be attached to more
than one CPU at a time. When a table