Entries are cleared from the TLB in accordance with the following rules:
1. All entries are cleared from the
TLB by the execution of PURGE TLB
and SET PREFIX and by CPU reset.
2. Selected entries are cleared from
all TLBs in the configuration by the execution of INVALIDATE PAGE TABLE ENTRY by any of the CPUs in the configuration.
3. Some or all TLB
cleared at times required by PURGE CPU reset, and
TABLE ENTRY. entries may be
other than those
TLB, SET PREFIX, INVALIDATE PAGE Programming Notes 1. Entries in the TLB may continue to
be used for translation after the
table entries from which they have been formed have become unattached
or invalid. These TLB entries are
not necessarily removed unless explicitly cleared from the TLB.
A change made to an attached and valid entry or a change made to a
table entry that causes the entry
to become attached and valid is reflected in the translation proc­ ess for the next instruction, or earlier than the next instruction, unless a TLB entry qualifies for
substitution for that table entry. However, a change made to a table
entry that causes the entry to become unattached or invalid is not necessarily reflected in the trans­
lation process until the TLB is cleared of entries which qualify
for substitution for that table
entry.
2. Exceptions associated with dynamic
address translation may be estab­ lished by a pretest for operand accessibility that is performed as
part of the initiation of instruc­ tion execution. Consequently, a
segment-translation or page-
translation exception may be
indicated when a table entry is invalid at the start of execution even if the instruction would have
validated the table entry it uses
and the table entry would have
appeared valid if the instruction was considered to process the oper­
ands one byte at a time. 3. A change made to an attached table
entry, except to set the I bit to
zero or to alter the rightmost bit of a page-table entry, may produce
unpredictable results if that entry
is used for translation before the
TLB is cleared of all copies of
that entry. The use of the new
value may begin between instructions or during the execution of an instruction, including the instruction that
caused the change. When an
instruction, such as MOVE (MVC),
makes a change to an attached table
entry, including a change that
makes the entry invalid, and subse­
quently uses the entry for
translation, a changed entry is being used without a prior clearing
of the entry from the TLB, and the
associated unpredictability of
result values and of exception
recognition applies.
Manipulation of attached table
entries may cause spurious table­
entry values to be recorded in a
TLB. For example, if changes are made piecemeal, modification of a
valid attached entry may cause a
partially updated entry to be recorded, or, if an intermediate value is introduced in the process
of the change, a supposedly invalid
entry may temporarily appear valid
and may be recorded in the TLB.
Such an intermediate value may be introduced if the change is made by
an I/O operation that is retried,
or if an intermediate value is introduced during the execution of
a single instruction.
As another example, if a segment­
table entry is changed to designate
a different page table and used without clearing the TLB, then the
new page-table entries may be fetched and associated with the old
page-table origin. In such a case, execution of INVALIDATE PAGE TABLE ENTRY designating the new page­ table origin will not necessarily
clear the page-table entries fetched from the new page table.
4. To facilitate the manipulation of
translation tables, INVALIDATE PAGE TABLE ENTRY is provided, which sets the I bit in a page-table entry to
one and clears all TLBs in the configuration of entries formed
from that table entry.
INVALIDATE PAGE TABLE ENTRY is
useful for setting the I bit to one in a page-table entry and causing
TlB copies of the entry to be
cleared from the TLB of each CPU in the configuration. The following
aspects of the TLB operation should
be considered when using INVALIDATE PAGE TABLE ENTRY. (See also the
programming notes following INVALI­
DATE PAGE TABLE ENTRY.) a. INVALIDATE PAGE TABLE ENTRY should be executed before
making any change to a page­
table entry other than changing
Chapter 3. Storage 3-37

the rightmost bit; otherwise,
the selective clearing portion
of INVALIDATE PAGE TABLE ENTRY may not clear the TLB copies of
the entry.
b. Invalidation of all the
page-table entries within a page table by means of INVALI­
DATE PAGE TABLE ENTRY does not
necessarily clear the TLB of
the copies, if any, of the
segment-table entry designating
the page table. When it is
desired to invalidate and clear
the TLB of a segment-table
entry, the rules in note 5
below must be followed.
c. When a large number of
page-table entries are to be
invalidated at a single time,
the overhead involved in using PURGE TLB and in following the
rules in note 5 below may be
less than in issuing INVALIDATE
PAGE TABLE ENTRY for each
page-table entry.
5. Manipulation of table entries
should be in accordance with the
following rules. If these rules
are complied with, translation is
performed as if the table entries
from real storage were always used
in the translation process.
a. A valid table entry must not be
changed while it is attached to
any CPU except either to inval­
idate the entry, by using
INVALIDATE PAGE TABLE ENTRY or
to alter bit 15 of a page-table
entry.
b. When any change is made to a
table entry other than a change
to bit 15 of a page-table
entry, each CPU which may have
a TLB entry formed from that
entry must execute PURGE TLB or
SET PREFIX or perform CPU reset, after the change occurs
and prior to the use of that
entry for implicit translation
by that CPU, except that the
purge is unnecessary if the
change was made by using INVAL­
IDATE PAGE TABLE ENTRY. c. When any change is made to an
invalid table entry in such a way as to allow intermediate
valid values to appear in the entry, each CPU to which the
entry is attached must execute PURGE TLB or SET PREFIX or
perform CPU reset, after the
change occurs and prior to the
use of the entry for implicit
address translation by that CPU. 3-38 System/370 Principles of Operation d. When any change is made to a
segment-table or page-table
length, each CPU to which that
table has been attached must
execute PTLB after the length
has been changed but before
that table becomes attached
again to the CPU. Note that when an invalid page­
table entry is made valid without
introducing intermediate valid
values, the TLB need not be cleared
in a CPU which does not have any
usable TLB copies for that entry.
Similarly, when an invalid
segment-table entry is made valid
without introducing intermediate
valid values, the TLB need not be
cleared in a CPU which does not
have any usable TLB copies for that
segment-table entry and which does
not have any usable TLB copies for
the page-table entries attached by
it.
The execution of PURGE TLB and SET PREFIX may have an adverse effect
on the performance of some models. Use of these instructions should,
therefore, be minimized in conform­
ity with the above rules.
ADDRESS SUMMARY ADDRESSES TRANSLATED
Most addresses that are explicitly spec­
ified by the program and are used by the CPU to refer to storage for an instruc­
tion or an operand are logical addresses
and are subject to implicit translation
when DAT is on. Analogously, the corre­
sponding addresses indicated to the
program on an interruption or as the
result of executing an instruction are
logical. The operand address of LOAD REAL ADDRESS is explicitly translated,
regardless of whether the PSW specifies
the EC mode or BC mode, and regardless
of whether the EC-mode PSW specifies OAT on or off.
Translation is not applied to quantities
that are formed from the values speci­
fied in the Band D fields of an instruction but that are not used to
address storage. This includes operand
addresses in LOAD ADDRESS, MONITOR CALL, and the shifting and I/O instructions.
This also includes the addresses in
control registers 10 and 11 designating
the starting and ending locations for
PER.
With the exception of INSERT VIRTUAL STORAGE KEY and TEST PROTECTION, the
addresses explicitly designating storage
keys (operand addresses in SET STORAGE