CHAPTER 1. INTRODUCTION .•.. General-Purpose Design .•... Compatibility .. .. . .. Compatibility among System/370 ........•.. Compatibility between System/360 and System/370 ..
System Program . • . . . . Availability ...... • .. CHAPTER 2. ORGANIZATION Main Storage . . CPU ...•... . PSW ..... . • .
General Registers ....•. Floating-Point Registers Control Registers Vector Facility I/O .... ... Channel Sets . . . . Channels .......... . I/O Devices and Control Units Operator Facilities CHAPTER 3. STORAGE Storage Addressing ...••. Storage Addressing with
Extended Address Fields
Information Formats
Integral Boundaries ... Byte-Oriented-Operand Facility Address Types . • . • Absolute Address Real Address
Virtual Address Primary Virtual Address
Secondary Virtual Address Logical Address ..•. Instruction Address ...
Effective Address
Storage Key .........• Storage-Key 4K-Byte-Block
Facility ....... .
Storage Keys with Storage-Key 4K-Byte-Block facility Not Installed .......•• Storage Keys with Storage-Key
4K-Byte-Block Facility Installed ...•.•..• Storage-Key-Exception Control Storage-Key-Instruction
Extensions ..... . Protection ........ .
Key-Controlled Protection Segment Protection ..•••• Low-Address Protection ..•• Reference Recording Change Recording Prefixing •..• Address Spaces ASH Translation ....•..• ASN-Translation Controls ASN-Translation Tables ASN-first-Table Entries
ASN-Second-Table Entries
ASN-Translation Process ASN-First-Table Lookup
ASN-Second-Table Lookup
1-1
1-2
1-3
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1-3
1-4
1-4
2-1
2-3
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2-4
2-6
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2-6
3-1
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3-9 3-10 3-10 3-11
3-12
3-13
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3-14
3-14
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3-15
3-16
3-16 CONTENTS Recognition of Exceptions
during ASN Translation ASN Authorization ..• ASH-Authorization Controls Control Register 4 ASH-Second-Table Entry
Authority-Table Entries ASH-Authorization Process Authority-Table Lookup
Recognition of Exceptions
during ASH Authorization
Dynamic Address Translation
Translation Control Translation Modes Control Register 0 Control Register 1 Control Register 7
Translation Tables . . Segment-Table Entries Page-Table Entries Summary of
Dynamic-Address-Translation
Formats ........ .
Translation Process Effective Segment-Table Designation .. ... • Inspection of Control Register o ••••••••••••• Segment-Table Lookup •..• Page-Table Lookup ....• Formation of the Real Address
Recognition of Exceptions
during Translation •.•• Translation-Lookaside Buffer Use of the
Translation-Lookaside Buffer Modification of Translation
Tables •.•.. Address Summary .....
Addresses Translated
Handling of Addresses
Assigned Storage Locations CHAPTER 4. CONTROL . Stopped, Operating, Load, and Check-Stop States Stopped State Operating State Load State Check-Stop state Program-Status Word EC and BC Modes •••••.. Program-Status-Word Format in EC Mo de ••••••••• Program-Status-Word Format in BC Mode •..• Control Registers ••.• DAS Tracing •.•.. Protection for DAS Tracing Other Actions Associated with
DAS Tracing ....... . Serialization for DAS Tracing
Trace-Table Designation
Trace-Table-Entry Header
Interlocks •••.••. Trace Entry .••••• Program-Event Recording • Control-Register Allocation
3-17
3-17
3-17
3-17
3-17
3-18
3-18
3-19 3-20 3-20 3-22
3-22
3-23
3-24
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3-25
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3-27
3-27 3-30 3-30 3-31
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3-41
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4-3 4-3 4-4
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Operation · · · · · · · 4-16 Execution of Interruptible Identification of Cause 4-17 Instructions · · · · · 5-9 Priority of Indication 4-17 Exceptions to Nullification and
storage-Area Designation 4-18 Suppression · · · · · · · · · 5-11
PER Events · · · · · 4-19 Storage Change and Restoration
Successful Branching · · · 4-19 for DAT-Associated Access
Instruction Fetching · · · · 4-19 Exceptions · · · · · · · · 5-11
Storage Alteration · · · 4-19 Modification of DAT-Table
General-Register Alteration 4-20 Entries · · · · · · · · · · 5-12
Indication of PER Events Trial Execution for Editing Concurrently with Other Instructions and TRANSLATE 5-12
Interruption Conditions 4-20 Interlocked Update for
Direct Control · · · · · 4-23 Nullification and Suppression 5-12
Read-Write-Direct Facility 4-23 Dual-Address-Space Control 5-13
External-Signal Facility 4-23 Summary . · · · · · · · 5-13
Timing . . · · · · · · · · 4-23 DAS Functions · · · · · · 5-14
Time-of-Day Clock 4-23 Using Two Address Spaces 5-14
Format · · · · · · · 4-24 Changing to Other Spaces 5-14
states · · · · · 4-24 Moving Information · · · 5-15 Changes in Clock State · {t-25 Transferring Program Control 5-15
Setting and Inspecting the Handling Storage Keys and the Clock · · · · · · · · 4-25 PSW Key · · · · · · · · 5-16 TOD-Clock Synchronization 4-26 Program-Problem Analysis 5-17 Clock Comparator · · · · 4-27 DAS Authorization isms 5-17 CPU Timer · · · · · · · 4-28 Mode Requirements · · · 5-17
Interval Timer · · · · · · 4-29 Extraction-Authority Control 5-17
Externally Initiated Functions 4-30 PSW-Key Mask · · · · · · 5-18
Resets . · · · · 4-30 Secondary-Space Control 5-18 CPU Reset 4-33 Subsystem-Linkage Control 5-18 Initial CPU Reset 4-34 ASN-Translation Control 5-18 Subsystem Reset 4-34 Authorization Index 5-18 Program Reset · · 4-34 PC-Number Translation 5-21 Initial Program Reset 4-34 PC-Number Translation Control 5-21 Clear Reset · · · · 4-34 PC-Number Translation Tables 5-21 Power-On Reset · · · · 4-35 Linkage-Table Entries 5-21
Initial Program Loading 4-35 Entry-Table Entries · · · · 5-22
Store Status · · · · 4-37 PC-Number-Translation Process 5-22
Multiprocessing · · · · · · · 4-37 Linkage-Table Lookup · · · · 5-23
Shared Main Storage · · 4-38 Entry-Table Lookup · · · · 5-24 CPU-Address Identification 4-38 Recognition of Exceptions CPU Signaling and Response 4-38 during PC-Number Translation 5-24 Signal-Processor Orders · · · 4-38 Sequence of Storage References 5-24 Conditions Determining Response 4-40 Conceptual Sequence 5-24 Conditions Precluding Overlapped Operation of
Interpretation of the Order Instruction Execution 5-24 Code · · · · · · · · · 4-40 Divisible Instruction
Status Bits 4-41 Execution · · · · · · · · · 5-25 Channel-Set Switching 4-43 Interlocks for Virtual-Storage
References · · · · 5-25 CHAPTER 5. PROGRAM EXECUTION 5-1 Instruction Fetching 5-26
Instructions · · · · · · · · 5-2 DAT-Table Fetches 5-27 Operands · · · · · · · · · 5-2 Storage-Key Accesses 5-28
Instruction Format 5-3 Storage-Operand References 5-28
Register Operands · · · · · 5-4 Storage-Operand Fetch
Immediate Operands 5-4 References · · · · · · · · 5-29
Storage Operands · · · · 5-4 Storage-Operand store
Address Generation · · · · · · · 5-5 References · · · · 5-29
Sequential Instruction-Address Storage-Operand Update
Generation · · · · · · · 5-5 References · · · · · · 5-29
Operand-Address Generation 5-5 Storage-Operand Consistency 5-30 Branch-Address Generation 5-6 Single-Access References 5-30 Instruction Execution and Multiple-Access References 5-31
Sequencing · · · · · · · · 5-6 Block-Concurrent References 5-31
Decision Making · · · · · 5-6 Consistency Specification 5-31
Loop Control 5-6 Relation between Operand Subroutine Linkage · · · · 5-6 Accesses · · · · · · · · · · 5-32
Interruptions · · · · · 5-8 Other Storage References 5-33
Types of Instruction End; ng 5-8 Serialization · · · · · 5-33 Completion 5-9 CPU Serialization · · · 5-33
Suppression 5-9 Channel-Program Serialization 5-34
Nullification · · · · 5-9
Termination · · · 5-9 CHAPTER 6 . INTERRUPTIONS 6-1 I Interruptible Instructions 5-9 Interruption Action 6-2 \ Point of Interruption 5-9 Interruption Code 6-5
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