b. The general-register-alteration
event is indicated on the
initial execution and on each
resumption and does not depend
on whether or not the register
actually is changed.
c. The storage-alteration event is
indicated only data has
been stored in the designated
storage area by the portion of
the operation starting with the last initiation and ending with
the last byte transferred
before the interruption. No
special indication is provided
on premature interruptions as
to whether the event will occur again upon the resumption of
the operation. When the desig­
nated storage area is a single
byte location, a storage­
alteration event can be recognized only once in the
execution of MOVE LONG. 2. The following is an outline of the
general action a program must take
to delete multiple entries in the PER data for an interruptible
instruction so that only one entry
for each complete execution of the
instruction is obtained:
a. Check to see if the PER address is equal to the instruction
address in the old PSW and if
the last instruction executed
was interruptible.
b. If both conditions are met,
delete instruction-fetching and register-alteration events.
c. If both conditions are met and
the event is storage
alteration, delete the event if
some part of the remaining
destination operand is within
the designated storage DIRECT CONTROL The direct-control facility consists of
two facilities: (1) a read-write-direct
facility, including the two instructions
READ DIRECT and WRITE DIRECT and an
associated 27-line interface, and (2) an
external-signal facility with six
signal-in lines. These facilities oper­ ate independent of the facilities that
perform I/O operations. READ-WRITE-DIRECT FACILITY The READ DIRECT and WRITE DIRECT instructions use the 27-line interface
to provide timing signals and to trans­
fer a single byte of information,
normally for controlling and synchroniz­
ing purposes, between CPUs or between a CPU and an external device. The 27
lines are:
Number
Name of Lines Direction
Wri te out 1 Output Read out 1 Output Hold 1 Input
Signal out 8 Output Direct out 8 Output Direct in 8 Input
EXTERNAL-SIGNAL FACILITY The external-signal facility consists of
six signal-in lines and an external­
signal mask, which is bit 26 of control
register O. Each of the six signal-in
lines, when pulsed, sets up the condi­
tion for one of six distinct inter­
ruptions (see the section "External Signal" in Chapter 6, "Interruptions").
Note: Some model s prov i de the
external-signal facility without the
read-write-direct facility.
For a detailed description, see the
System/360 and System/370 Direct-Control and Exter'nal-Interrupti on Features
Original £9..uipment Manufi'lcturers' Infor­ mation, GA22-6845.
TIMING
The timing facilities include four
facilities for measuring time: the TOO clock, the clock comparator, the CPU timer, and the interval timer.
In a multiprocessing configuration, a
single TOO clock may be shared by more
than one CPU, or each CPU may have a
separate TOO clock. However, each CPU has a separate clock comparator, CPU timer, and timer. TIME-OF-DAY CLOCK The time-of-day (TOD) clock provides a
high-resolution measure of real time
suitable for the indication of date and
time of day. The cycle of the clock is
approximately 143 years.
In an installation with more than one CPU, each CPU may have a separate TOD clock, or more than one CPU may share a
clock, depending on the model. In all Chapter 4. Control 4-23

cases, each CPU has access to a single
clock.
The TOO clock is a binary counter with the format shown in the following illus­
tration. The bit positions of the clock
are numbered 0 to 63, corresponding to
the bit positions of a 64-bit unsigned
binary integer.
o
1 microsecond---, .J.. I I 51 63
In the basic form, the TOO clock is incremented by adding a one in bit posi­
tion 51 every microsecond. In models
having a higher or lower resolution, a
different bit position is incremented at
such a frequency that the rate of
advancing the clock is the same as if a one were added in bit position 51 every
microsecond. The resolution of the TOO clock is such that the incrementing rate
is comparable to the instruction­
execution rate of the model.
A TOO clock is said to be in a partic­
ular multiprocessing configuration if at
least one of the CPUs which shares that
clock is in the configuration. Thus, it is possible for a single TOO clock to be
in more than one configuration. Conversely, if all CPUs having access to a particular TOO clock have been removed
from a particular configuration, then
the TOO clock is no longer considered to
be in that configuration.
When more than one TOO clock exists in
the configuration, the stepping rates
are synchronized such that all TOO clocks in the configuration are incre­
mented at exactly the same rate.
When incrementing of the clock causes a carry to be propagated out of bit posi­
tion 0, the carry is ignored, and count­
ing continues from zero. The program is
not alerted, and no interruption condi­
tion is generated as a result of the
overflow.
The operation of the clock is not
affected by any normal activity or event
in the system. Incrementing of the
clock does not depend on whether the
wait-state bit of the PSW is one or
whether the CPU is in the operating,
load, stopped, or check-stop state. Its
operation is not affected by CPU, initial-CPU, program, initial-program,
or clear resets or by initial program
loading. Operation of the clock is also
not affected by the setting of the rate
control or by an initial-microprogram-
4-24 System/370 Principles of Operation loading operation. Depending on the
model and the configuration, a TOO clock
mayor may not be powered independent of
a CPU that accesses it. States The following states are distinguished
for the TOO clock: set, not set,
stopped, error, and not operational.
The state determines the condition code
set by execution of STORE CLOCK. The
clock is incremented, and is said to be
running, when it is in either the set
state or the not-set state.
Not-Set State: l.Jhen the power for the
clock is turned on, the clock is set to zero, and the clock enters the not-set
state. The clock is incremented when in
the not-set state. When the clock is in the not-set state,
execution of STORE CLOCK causes condi­
tion code 1 to be set and the current
value of the running clock to be stored. State: The clock enters the
stopped state when SET CLOCK is executed
on a CPU accessing that clock and the
clock is set. This occurs when SET CLOCK is executed without encountering
any exceptions and any manual TOO-clock control in the configuration is set to the enable-set position. The clock can
be placed in the stopped state from the set, not-set, and error states. The
clock is not incremented while in the
stopped state.
When the clock is in the stopped state,
execution of STORE CLOCK on a CPU accessing that clock causes condition
code 3 to be set and the value of the
stopped clock to be stored. Set State: The clock enters the set
state only from the stopped state. The
change of state is under control of the
TOD-clock-sync-control bit, bit 2 of
control register 0, in the CPU which
most recently caused that clock to enter
the stopped state. If the bit is zero
or the TOO-clock-synchronization facili­
ty is not installed, the clock enters
the set state at the completion of
execution of SET CLOCK. If the bit is
one, the clock remains in the stopped
state until the bit is set to zero on
that CPU, until another CPU executes a SET CLOCK instruction affecting the
clock, or until any other clock in the
configuration is incremented to a value
of all zeros in bit positions 32-63. If
any clock is set to a value of all zeros
in bit positions 32-63 and enters the
set state as the result of a signal from
another clock, the updating of bits
32-63 of the two clocks is in synchro­
nism.