CHAPTER CONTROL stopped, Operating, Load, and Check-Stop States ••••••••••• 4-2 Stopped State •.••.••.••••••••.•••.••••.•••••••••••.••••• 4-2 Operat i ng State .••••••••.••.••.••••••••••••••••••••••••• 4-2
load State ......•••...•••.•••.••••.•••.•••••••••••••.••• 4-3 Check-Stop State •...•..••••.•.••••••••.••••••••.•••••••. 4-3 Program-Status Word .••..•••••••.•••••••..•••••••••••..•.•. 4-3 EC and BC Modes ••..••.•••.•••.••••••••..•••••••••••.•••• 4-4 Program-Status-Word Format in EC Mode ..••••••••••••.••.• 4-6 Program-Status-Word Format in BC Mode •.••••••.•••••.•••. 4-8 Control Registers .••••..•.••.....•.••••..••••.••••.....••• 4-8 DAS Tracing •..•.•••.••..••..••••••••••••.••••••••••••••••• 4-11
Protection for DAS Tracing •..•.•..••....••..•.•.•••.•• 4-13 Other Actions Associated with DAS Tracing ••••.••.••.•• 4-13 Serialization for DAS Tracing ••..•••....•••••••••••..• 4-13
Trace-Table Designation •••.•.••••••••..•.••••.•.•••.••.• 4-13
Trace-Table-Entry Header •.•....•••••••.••.•.•.•.••.••..• 4-13
Interlocks ••....•.....•••.•.•.•.•••..••••...•.•.••..•• 4-14 Trace Entry •••...•.............••......•••...•.•.•••..•. 4-14 Program-Event Recording .•..•...•...••.......••............ 4-15 Control-Register Allocation ....•.••....•..•...•.••.••..• 4-15 Operati on .•......•...•.•.•••.••••..•...•.•..•..••.••.••. 4-16
Identification of Cause ....••........•.••.•.•.•.•.•.•• 4-17 Priority of Indication ••.•...•.........•.••••••••..... 4-17 Storage-Area Designation •...•..•..•••....••.••.•.••••••. 4-18 PER Events .......................••.....•.•••.•.••..••.. 4-19 Successful Branching .••.•..••....•....••..•.•..•.•...• 4-19
Instruction Fetching .•..........•....•.....••..•..•..• 4-19 Storage Alteration ..••.........•......••.•.....•...... 4-19
General-Register Alteration ..•.•...•.•...•.•..•..•.••• 4-20 Indication of PER Events Concurrently with Other Interruption Conditions ..........•......•..•.•..•..••.• 4-20 Di rect Control ..........••....................••...•••.... 4-23
Read-Write-Direct Facility .............•.•.....••......• 4-23 External-Signal Facility ....•..•••...•.•..•.....•..•••.. 4-23
Timing .....•........•................•....•.•.•••..•....•• 4-23 Time-of-Day Clock ......•...............•.........•••..•. 4-23 Format .....•..•............••...•....•••.•...••....... 4-24 States ......................•...••.....•.••.•......••. 4-24 Changes in Clock State ..•.......•......•..•..•.••..... 4-25 Setting and Inspecting the Clock ............•..•.•...• 4-25 TOO-Clock Synchronization ............•...•...••.......•. 4-26 Clock Comparator ..........•..........•.•...•..•......... 4-27 CPU T 1 mer ....•.........••.........•..•...•.•..•.•••..... 4-28
Interval Timer .........••.........•..•.................. 4-29 Externally Initiated Functions ...........•.•............•. 4-30 Resets ...•......•..................•...•.•...••.•.....•. 4-30 CPU Reset .............•....•.....••.........•.•..••••. 4-33 Inrtial CPU Reset ...•........•.•.•.•.••.••...••.....•• 4-34 Subsystem Reset ......................•.....•......•.•. 4-34 Program Reset .........••....•....•••.....•••..•....••. 4-34
Initial Program Reset .......••.•..•••..••...•••...•.•. 4-34 Clear Reset .........••..•..........•.....••...•••••... 4-34 Power-On Reset ........•.••.......••.•....•.•••.•..•.•. 4-35
Initial Program loading ...•.....••..••.•.••••..•...•..•• 4-35
store Status .•..•••...•.•.•......••.•..••.••••..••.•..•. 4-37
Multiprocessing ...•.•.•.••......•...•.•....••.•.•.••..•.•• 4-37 Shared Main Storage .....•.•......•.•••.•••.•.•..•••••.•. 4-38 CPU-Address Identification ....•..•..........••..•.....•. 4-38 CPU Signaling and Response .••.....•.........•.........•... 4-38 Signal-Processor Orders .•......•....•..•..•••......••.•. 4-38
Conditions Determining Response ....•..•..•........•••..• 4-40 Conditions Precluding Interpretation of the
Order Code ...............................•••.•••...•. 4-40 Status Bi ts .........•.•......•.••....•...•...•.••...•• 4-41 Channel-Set Switching .....•......•..•••...•..••....••.•..• 4-43 Chapter 4. Control 4-1

This chapter describes 1n facilities for controlling,
and recording the operation
more CPUs. detail the
measuring,
of one or STOPPED, OPERATING, LOAD, AND CHECK-STOP STATES The stopped, operating, load, and
check-stop states are four mutually
exclusive states of the CPU. When the CPU is in the stopped state,
instructions and interruptions, other
than the restart interruption, are not
executed. In the operating state, the CPU executes instructions and takes interruptions, subject to the control of
the program-status word (PSW) and control registers, and in the manner specified by the setting of the
operator-facility rate control. The CPU is in the load state during the initial-program-loading operation. The CPU enters the check-stop state only as the result of machine malfunctions.
A change between these four CPU states
can be effected by use of the operator
facilities or by acceptance of certain SIGNAL PROCESSOR orders addressed to
that CPU. The states are not controlled
or identified by bits in the PSW. The
stopped, load, and check-stop states are indicated to the operator by means of the manual indicator, load indicator, and check-stop indicator, respectively. Th8se three indicators are off when the CPU is in the operating state. The CPU timer is updated when the CPU is in the operating state or the load state. The TOO clock is not affected by
the state of any CPU. The interval timer is updated only when the CPU is in the operating state. STOPPED STATE The CPU changes from the operating state
to the stopped state by means of the stop function. The stop function is pc;rformed vJhen: • • The stop key is activated while the CPU is in the operating state. The CPU accepts a stop or stop­
and-store-status order specified by a SIGNI\L PROCESSOR instruction addressed to this CPU while it is in the operating state. The CPU has finished the execution
of a unit of operation initiated by
performing the start function with the rate control set to the instruction-step position.
4-2 System/370 Principles of Operation When the stop function 1S performed, the
transition from the operating to the
stopped state occurs at the end of the
current unit of operation. When the
wait-state bit of the PSW is one, the
transition takes place immediately, provided no interruptions are pending
for which the CPU is enabled. In the case of interruptible instructions, the
amount of data processed in a unit of
operation depends on the particular instruction and may depend on the model.
Before entering the stopped state by
means of the stop function, all pending allowed interruptions are taken while
the CPU is still in the operating state.
They cause the old PSW to be stored and
the new PSW to be fetched before the
stopped state is entered. While the CPU i sin the stopped state, interrupt ion
conditions remain pending.
The CPU is also placed in the stopped
state when: • The CPU reset is completed. Howev­
er, when the reset operation is performed as part of initial program loading for this CPU, then
the CPU is placed in the load state
and does not necessarily enter the
stopped state. • An address comparison indicates
equality and stopping on the match
is specified.
The execution of resets is described in the section "Resets" in this chapter,
and address comparison is described in
the sect; on Controls" in Chapter 12, "Operator Facilities." If the CPU is in the stopped state when an INVALIDATE PAGE TABLE ENTRY instruc­
tion is executed on another CPU in the configuration, the invalidation may be
performed immediately or may be delayed until the CPU leaves the stopped state. OPERATING STATE The CPU changes from the stopped state
to the operating state by means of the start function or when a restart inter­ ruption (5ee Chapter 6) occurs.
The start function is performed if the CPU is in the stopped state and (1) the
start key associated with that CPU is activated or (2) that CPU accepts the 5tart order specified by a SIGNAL PROCESSOR instruction addressed to that CPU. The effect of performing the start
function is unpredictable when the stopped state has been entered by means of a reset. L-Jhen the rate control is se"t to the process position and the start function