is performed, the CPU starts operating
at normal speed. When the rate control
is set to the instruction-step position
and the wait-state bit is zero, one
instruction or, for interruptible
instructions, one unit of operation is
executed, and all pending allowed inter
ruptions are taken before theCPU returns to the stopped state. When the
rate control is set to the instruction
step position and the wait-state bit isone, the start function causes no
instruction tobe executed, but all
pending allowed interruptions are taken
before the CPU returns to the stopped
state.
LOAD STATEThe CPU enters the load state when the load-normal or load-clear key ;s acti vated. (See the section "Initial
Program loading" in this chapter.) If
the initial-program-Ioading operationis completed successfully, the CPU changes
from the state to the operating
state, provided the rate control is set
to the process position; if the rate
control is set to the instruction-step
position, the CPU changes from the load
state to the stopped state.
CHECK-STOP STATE
The check-stop state, which theCPU enters on certain types of machine malfunction, is described in Chapter 11, nl1achine-Check Hundling." The CPU leaves the check-stop state when CPU reset is ProqramminQ Notes 1. Except for the relationship between execution time and real time, the execution of a program is not affected by stopping the CPU. 2. When, because of a malfunc an invalid address in the
prefix register, oran incomplete
READ DIRECT instruction, theCPU is unable to end the execution of an
instruction, the stop function is
ineffective,and a reset function has to be invoked instead. A simi lar situation occurs when an unending string of interruptions results from a PSW with a PSW-format error of the type that
is recognized early, or from a
persistent interruption condition,
such as one due to the CPU timer.
3. Pending I/O operations may be
initiated, and active I/O oper
ations continue to suspension or
completion, after theCPU enters
the stopped state. The inter-
ruption conditions due to
suspension or completion of I/O
operations remain pending when the
CPU is in the stopped state.
PROGRAM-STATUS WORD
The current program-status word (PSW) in
the CPU contains information required
for the execution of the currentlyactive program. The PSW is 64 bits in
length and includes the instruction
address, condition code, and other
control fields. In general, thePSW is used to control instruction sequencing
and to hold and indicate much of the
status of theCPU in relation to the
program currently being executed. Addi
tional control and status information is
contained in control registers and
permanently assigned storage locations.
The status of theCPU can be changed by
loading a newPSW or part of a PSW. Control is switched during an inter
ruption of theCPU by storing the
currentPSW, so as to preserve the
status of theCPU, and then loading a new Execution of LOAD PSW, or the successful
conclusion ofthe initial-progrDm loading sequence, introduces a new PSW. The instruction address is updated by sequential instruction Qxecution and replaced by successful branches. Other instructions are provided which operate on a portion of the PSW. The figure "Operati ons on Fi eids" sumr:'lari .::es these instructions. A new or modified PSW becomes active (that is, tha information introduced
intothe current PSW assumes control over the CPU) when the interruption or
theexecution of an instruction that changes the PSW is The interruption for PER associated with an instruction changes the PSW occurs
under control ofthe PER mask that is effective at the beginning of the opera tion. Bits 0-7 of the PSW are collectively
referred to as the system mask.
Chapter 4. Control 4-3
at normal speed. When the rate control
is set to the instruction-step position
and the wait-state bit is zero, one
instruction or, for interruptible
instructions, one unit of operation is
executed, and all pending allowed inter
ruptions are taken before the
rate control is set to the instruction
step position and the wait-state bit is
instruction to
pending allowed interruptions are taken
before the CPU returns to the stopped
state.
LOAD STATE
Program loading" in this chapter.) If
the initial-program-Ioading operation
from the
state, provided the rate control is set
to the process position; if the rate
control is set to the instruction-step
position, the CPU changes from the load
state to the stopped state.
CHECK-STOP STATE
The check-stop state, which the
prefix register, or
READ DIRECT instruction, the
instruction, the stop function is
ineffective,
is recognized early, or from a
persistent interruption condition,
such as one due to the CPU timer.
3. Pending I/O operations may be
initiated, and active I/O oper
ations continue to suspension or
completion, after the
the stopped state. The inter-
ruption conditions due to
suspension or completion of I/O
operations remain pending when the
CPU is in the stopped state.
PROGRAM-STATUS WORD
The current program-status word (PSW) in
the CPU contains information required
for the execution of the currently
length and includes the instruction
address, condition code, and other
control fields. In general, the
and to hold and indicate much of the
status of the
program currently being executed. Addi
tional control and status information is
contained in control registers and
permanently assigned storage locations.
The status of the
loading a new
ruption of the
current
status of the
conclusion of
into
the
under control of
referred to as the system mask.
Chapter 4. Control 4-3