• Comparing the rightmost 32 bits of
each clock in the configuration.
An unequal condition is signaled by
an external interruption with the
interruption code 1003 hex, indi­ cating the TOO-clock-sync-check
condition. • Setting a TOO clock to the stopped
state. • Causing a stopped clock, with the
TOO-clock-sync-control bit set to
one, to start incrementing when
bits 32-63 of any running clock in
the configuration are incremented
to zero. This permits the program
to synchronize all clocks to any
particular clock without requiring
special operator action to select a
"master clock" as the source of the
clock-synchronization pulses.
Programming Notes
1. TOO-clock synchronization provides
for checking and synchronizing only
the rightmost bits of the TOO clock. The program must check for
synchronization of the leftmost
bits and must communicate the
leftmost-bit values from one CPU to
another in order to correctly set
the TOO-clock contents.
2. The TOO-clock-sync-check external
interruption can be used to deter­
mine the number of TOO clocks in
the configuration. CLOCK COMPARATOR The clock comparator provides a means of
causing an interruption when the TOO­ clock value exceeds a value specified by
the program.
In a configuration with CPU, each CPU has a
comparator.
more than one
separate clock
The clock comparator has the same format
as the TOO clock. In the basic form,
the clock comparator consists of bits 0-47, which are compared with the corre­
sponding bits of the TOO clock. In some
models, higher resolution is obtained by
providing more than 48 bits. The bits
in positions provided in the clock
comparator are compared with the corre­
sponding bits of the clock. When the
resolution of the clock is less than
that of the clock comparator, the
contents of the clock comparator are
compared with the clock value as this
value would be stored by executing STORE CLOCK. The clock comparator causes an external
interruption with the interruption code 1004 hex. A request for a clock­
comparator interruption exists whenever
either of the following conditions
exists:
1. The TOO clock is running and the
value of the clock comparator is
less than the value in the compared
portion of the clock, both values being considered unsigned binary
integers. Comparison follows the
rules of unsigned binary
arithmetic.
2. The TOO clock is in the error state
or the not-operational state.
A request for a clock-comparator inter­
ruption does not remain pending when the
value of the clock comparator is made
equal to or greater than that of the TOO clock or when the value of the TOO clock
is made less than the clock-comparator
value. The latter may occur as a result
of the TOO clock either being set or
wrapping to zero.
The clock comparator can be inspected by
executing the instruction STORE CLOCK COMPARATOR and can be set to a specific
value by executing the SET CLOCK COMPA­ RATOR instruction.
The contents of the clock comparator are
initialized to zero by initial CPU reset. Programming Notes
1. An interruption request for the
clock comparator persists as long
as the clock-comparator value 1S
less than that of the TOO clock or
as long as the TOO clock is in the
error state or the not-operational
state. Therefore, one of the
following actions must be taken
after an external interruption for
the clock comparator has occurred
and before the CPU is again enabled
for external interruptions: the
value of the clock comparator has
to be replaced, the TOO clock has
to be set, the TOO clock has to
wrap to zero, or the clock­
comparator-subclass mask has to be
set to zero. Otherwise, loops of
external interruptions are formed.
2. The instruction STORE CLOCK may
store a value which is greater than
that in the clock comparator, even
though the CPU is enabled for the
clock-comparator interruption.
This is because the TOO clock may
be incremented one or more times
between when instruction execution
is begun and when the clock value
is accessed. In this situation, Chapter 4. Control 4-27

the interruption occurs
execution of STORE completed. CPU TIMER
when CLOCK The CPU timer provides a means for meas­
uring elapsed CPU time and for causing
an interruption when a specified amount
of time has elapsed.
In a configuration with more than one CPU, each CPU has a separate CPU timer.
The CPU timer is a binary counter with a
format which is the same as that of the TOO clock, except that bit 0 is consid­
ered a sign. In the basic form, the CPU timer is decremented by subtracting a
one in bit position 51 every
microsecond. In models having a higher
or lower resolution, a different bit
position is decremented at such a
frequency that the rate of decrementing
the CPU timer is the same as if a one
were subtracted in bit position 51 every
microsecond. The resolution of the CPU timer is such that the stepping rate is
comparable to the instruction-execution
rate of the model.
The CPU timer requests an external
interruption with the interruption code 1005 hex whenever the CPU-timer value is
negative (bit 0 of the CPU timer is
one). The request does not remain pend­
ing when the CPU-timer value is changed
to a nonnegative value.
When both the CPU timer and the TOO clock are running, the stepping rates
are synchronized such that both are
stepped at the same rate. Normally,
decrementing the CPU timer is not
affected by concurrent I/O activity.
However, in some models the CPU timer
may stop during extreme I/O activity and
other similar interference situations.
In these cases, the time recorded by the CPU timer provides a more accurate meas­
ure of the CPU time used by the program
than would have been recorded had the CPU timer continued to step.
The CPU timer is decremented when the CPU is in the operating state or the
load state. When the manual rate
control is set to instruction step, the CPU timer is decremented only during the
time in which the CPU is actually
performing a unit of operation.
However, depending on the model, the CPU timer mayor may not be decremented when
the TOD clock is in the error, stopped,
or not-operational state.
Depending on the model, the CPU timer
mayor may not be decremented when the CPU is in the check-stop state.
4-28 Systam/370 Principles of Operation The CPU timer can be inspected by
executing the instruction STORE CPU TIMER and can be set to a specific value
by executing the SET CPU TIMER instruc­
tion.
The CPU timer is set to zero by initial CPU reset.
1.
2.
3.
4.
The CPU timer in association with a
program may be used both to measure CPU-execution time and to signal
the end of a time interval on the
cpu.
The time measured for the execution
of a sequence of instructions may
depend on the effects of such
things as I/O interference, the
availability of pages, and instruc­
tion retry. Hence, repeated
measurements of the same sequence
on the same installation may
differ.
The fact that a CPU-timer inter­
ruption does not remain pending
when the CPU timer is set to a
positive value eliminates the prob­
lem of an undesired interruption.
This would occur if, between the
time when the old value is stored
and a new value is set, the CPU is
disabled for CPU-timer inter­
ruptions and the CPU timer value
goes from positive to negative.
The fact that CPU-timer inter­
ruptions are requested whenever the CPU timer is negative (rather than
just when the CPU timer goes from
positive to negative) eliminates
the requirement for testing a value
to ensure that it is positive
before setting the CPU timer to
that value.
As an example, assume that a
program being timed by the CPU timer is interrupted for a cause
other than the CPU timer, external
interruptions are disallowed by the
new PSW, and the CPU-timer value is
then saved by STORE CPU TIMER.
This value could be negative if the CPU timer went from positive to
negative since the interruption.
Subsequently, when the program
being timed is to continue, the CPU timer may be set to the saved value
by SET CPU TIMER. A CPU-timer interruption occurs immediately
after external interruptions are
again enabled if the saved value
was negative.
The persistence
interruption
however, that
of the CPU-timer­ request means,
after an external