interruption for the CPU timer has
occurred, the value of the CPU timer has to be replaced, the value
in the CPU timer has to wrap to a
positive value, or the CPU-timer­ subclass mask has to be set to zero
before the CPU is again enabled for
external interruptions. Otherwise, loops of external interruptions are
formed.
5. The instruction STORE CPU TIMER may
store a negative value even though
the CPU is enabled for the inter­
ruption. This is because the CPU­ timer value may be decremented one
or more times between when instruc­
tion execution is begun and when
the CPU timer is accessed. In this
situation, the interruption occurs
when the execution of STORE CPU TIMER is completed.
INTERVAL TIMER
The interval timer is a binary counter
that occupies a word at real storage
location 80 and has the following
format: IS I o r- 1/300 second I I 23 31
The interval timer is treated as a
32-bit signed binary integer. In the
basic form, the contents of the interval
timer are decremented by one in both bit
positions 21 and 22 every 1/50 of a
second, or the interval-timer contents
are decremented by one in both bit posi­
tions 21 and 23 every 1/60 of a second.
Higher resolution of timing may be
obtained in some models by counting with
higher frequency in other bit positions.
In each case, the frequency is adjusted
so that bits to the left of bit position
23 change as if bit position 23 were
being decremented by one every 1/300 of
a second. The cycle of the interval
timer is approximately 15.5 hours.
In a configuration with more than one CPU, each CPU has an interval timer.
The interval timer causes an external
interruption, with bit 8 of the inter­
ruption code set to one and bits 0-7 set
to zeros. Bits 9-15 of the interruption
code are zeros unless set to ones for
another condition that is concurrently
indicated.
A request for an interval-timer inter­ \ ruption is generated whenever the I interval-timer value is decremented from
a positive or zero number to a negative
number. The request is preserved and
remains pending in the CPU until it is
cleared by an interval-timer inter­
ruption or a CPU reset. The overflow
occurring as the interval-timer value is
decremented from a large negative number
to a large positive number is ignored.
The interval timer is not necessarily
synchronized with the TOO clock.
The interval-timer contents are updated
at the appropriate frequency whenever
other machine activity permits. The
updating occurs only between instruction
executions, except that the interval
timer may be updated between units of
operation of an interruptible instruc­
tion, such as MOVE LONG. An updated
interval-timer value is normallyavail­
able at the end of each instruction
execution. When the execution of an
instruction, I/O data transmission, or
other machine activity causes updating
to be delayed by more than one period,
the contents of the interval timer may
be decremented by more than one unit in a single updating cycle. Interval-timer
updating may be omitted when such delay
is extreme. The program is not alerted
when omission of updating causes the
real-time count to be lost.
When the contents of the interval timer
are fetched by a channel or another CPU, or when they are used as the source of
an instruction, the result is unpredict­
able. Similarly, storing by a channel
or another CPU into the interval timer
causes the contents of the interval
timer to be unpredictable. This unpre­
dictability is true even for the case of COMPARE AND SWAP or COMPARE DOUBLE AND SWAP when executed by another CPU. The interval timer is not decremented
when the manual interval-timer control
is set to the disable position. The
interval timer is also not decremented
when the CPU is not in the operating
state or when the manual rate control is
set to the instruction-step position.
Depending on the model, the interval
timer mayor may not be decremented when
the TOO clock is in the error, or not-operational state.
When the TOO clock accessed by a CPU is
set or changes state, interruption
conditions pending for the interval
timer mayor may not be recognized for
up to 1.048576 seconds after the change.
Programming Notes 1. The value of the interval timer is
accessible by fetching the word at
real location 80 as an operand,
provided the location is not
protected against fetching. It may
be changed at any time by storing a Chapter 4. Control 4-29

word at real location 80. When
real location 80 is protected, any
attempt by the program to change
the value of the interval timer
causes a program interruption for
protection exception.
2. The value of the interval timer may
be changed without losing the
real-time count by storing the new
value at real locations 84-87 and
then copying the contents of real
locations 80-87 to real locations
76-83 by means of the MOVE (MVC) instruction. Thus, in a single
operation, the new interval-timer
value is placed at real locations 80-83, and the old value is made
available at real locations 76-79.
If any means other than the
instruction MOVE (MVC) are used to
interrogate and then replace the
value of the interval timer,
including MOVE LONG or two separate
instructions, the program may lose
a time increment when an updating
cycle occurs between fetching and
storing.
logical locations 84-87 are used as
the trace-table designation by DAS
tracing. If the above means for
updating the interval timer by
using MOVE are used in a system
which also uses DAS tracing, and if logical location 84 maps to real
location 84, then the program must
restore the contents of the word at
real location 84 after updating the
interval timer.
3. When the value of the interval
timer is to be recorded on an I/O device, the program should first
store the interval-timer value in a
temporary storage location to which
the I/O operation subsequently
refers. When a channel program
fetches from locations 80-83, the
value obtained is unpredictable. EXTERNAllY INITIATED FUNCTIONS RESETS
Seven reset functions are provided: • CPU reset • Initial CPU reset • Subsystem reset 4-30 System/370 Principles of Operation • Program reset • Initial program reset • Clear reset • Power-on reset CPU reset provides a means of clearing
equipment-check indications and any
resultant unpredictability in the CPU state with the least amount of informa­
tion destroyed. In particular, it is
used to clear check conditions when the CPU state is to be preserved for analy­
sis or resumption of the operation.
Initial CPU reset provides the functions
of CPU reset together with initializa­
tion of the current PSW, CPU timer,
clock comparator, prefix, and control
registers.
Subsystem reset provides a means for
clearing floating interruption condi­
tions and for initializing channel-set
connections as well as for invoking
I/O-system reset. Program reset and initial program reset
cause CPU reset and initial CPU reset,
respectively, to be performed and cause
I/O-system reset to be performed (see
the section "I/O-System Reset" in Chap­ ter 13, "Input/Output Operations"). Clear reset causes initial CPU reset and
subsystem reset to be performed and,
additionally, clears or initializes all
storage locations and registers in all CPUs in the configuration, with the
exception of the TOO clock. Such clear­
ing is useful in debugging programs and
in ensuring user privacy. Clearing does
not affect external storage, such as
direct-access storage devices used by
the control program to hold the contents
of unaddressable pages.
The power-on-reset sequences for the TOO clock, main storage, and channels may be
included as part of the CPU power-on
sequence, or the power-on sequence for
these units may be initiated separately. CPU reset, initial CPU reset, SUbsystem
reset, and clear reset may be initiated
manually by using the operator facili­
ties (see Chapter 12, "Operator Facili­
ties"). Initial CPU reset is part of
the initial-program-Ioading function.
The figure "Manual Initiation of Resets"
summarizes how these four resets are
manually initiated. Power-on reset is
performed as part of turning power on.
The reset actions are tabulated in the
figure "Summary of Reset Actions." For
information concerning what resets can
be performed by the SIGNAL PROCESSOR instruction, see the section "Signal­ Processor Orders" in this chapter.