The orders are defined as follows: Sense: The addressed CPU presents its
status to the issuing CPU (see the
section "Status Bits" in this chapter
for a definition of the bits). No other
action is caused at the addressed CPU. The status, if not all zeros, is stored
in the general register designated by
the R, field of the SIGNAL PROCESSOR instruction, and condition code 1 is
set; if all status bits are zeros,
condition code 0 is set.
External Call: An external-call
external-interruption condition is
generated at the addressed CPU. The
interruption condition becomes pending
during the execution of SIGNAL PROCESSOR. The associated interruption
occurs when the CPU is enabled for that
condition and does not necessarily occur
during the execution of SIGNAL PROCESSOR. The address of the CPU send­
ing the signal is provided with the
interruption code when the interruption
occurs. Only one external-call condi­
tion can be kept pending in a CPU at a time. The order is effective only when
the addressed CPU is in the stopped or
the operating state.
Emergency Signal: An emergency-signal
external-interruption condition is generated at the addressed cpu. The
interruption condition becomes pending
during the execution of SIGNAL PROCESSOR. The associated interruption
occurs when the CPU is enabled for that
condition and does not necessarily occur
during the execution of SIGNAL PROCESSOR. The address of the CPU send­
ing the signal is provided with the
interruption code when the interruption
occurs. At anyone time the receiving CPU can keep pending one emergency­
signal condition for each CPU in the
configuration, including the receiving CPU itself. The order is effective only
when the addressed CPU is in the stopped
or the operating state. Start: The addressed CPU performs the
start function (see the section "Stopped, Operating, Load, and Check­ Stop states" in this chapter). The CPU does not necessarily enter the operating
state during the execution of SIGNAL PROCESSOR. The order is effective only
when the addressed CPU is in the stopped
state. The effect of performing the
start function is unpredictable when the
stopped state has been entered by reset. Stop: The addressed CPU performs the
stop function (see the section "Stopped, Operating, Load, and Check-Stop States" in this chapter). The CPU does not
necessarily enter the stopped state
during the execution of SIGNAL PROCESSOR. The order is effective only
when the CPU is in the operating state.
Restart: The addressed CPU performs the restart operation (see the section
"Restart Interruption" in Chapter 6, "Interruptions"). The CPU does not
necessarily perform the operation during
the execution of SIGNAL PROCESSOR. The
order is effective only when the
addressed CPU is in the stopped or the
operating state.
Initial Program Reset: The addressed CPU performs initial program reset (see
the section "Resets" in this chapter).
The execution of the reset does not
affect other CPUs. The reset operation
is not necessarily completed during the
execution of SIGNAL PROCESSOR. Program Reset: The addressed CPU performs program reset (see the section "Resets" in this chapter). The execution of the reset does not affect
other CPUs. The reset is not
necessarily completed during the
execution of SIGNAL PROCESSOR. stop and Store Status: The addressed CPU performs the stop function, followed
by the store-status function (see the
section "Store Status" in this chapter).
The CPU does not necessarily complete
the operation, or even enter the stopped
state, during the execution of SIGNAL PROCESSOR. The order is effective only
when the addressed CPU is in the stopped
or the operating state.
Initial Microprogram Load (IML): The
addressed CPU performs initial program
reset and then initiates the IML func­
tion. The IML function is the same as
that which is performed as part of manu­
al initial microprogram loading. If the
IML function is not provided on the addressed CPU, the order code is treated as unassigned and invalld. The opera­ tion is not necessarily completed during
the execution of SIGNAL PROCESSOR. Initial CPU Reset: The addressed CPU performs -mitial CPU reset (see the
section "Resets" in this chapter). The execution of the reset does not affect
other CPUs and does not cause I/O to be reset. If the initial-CPU-reset order
is not provided on the addressed CPU, the order is treated as unassigned and
invalid. The reset operation is not
necessarily completed during the of SIGNAL PROCESSOR. CPU Reset: The addressed CPU performs CPU reset (see the section "Resets" in
this chapter). The execution of the reset does not affect other CPUs and
does not cause I/O to be reset. If the CPU-reset order is not provided on the addressed CPU, the order is treated as
unassigned and The reset oper­ ation is not necessarily completed
during the execution of SIGNAL PROCESSOR. Chapter 4. Control 4-39

Programming Note
For a discussion on the relative
performance of the SIGNAL PROCESSOR orders, see the programming note follow­
ing the instruction SIGNAL PROCESSOR in Chapter 10, "Control Instructions." CONDITIONS DETERMINING RESPONSE Conditions Precluding Interpretation of
the Order Code The following situations preclude the
initiation of the order. The sequence
in which the situations are listed is
the order of priority for indicating
concurrently existing situations:
1. The access path to the addressed CPU is busy because a concurrently
executed SIGNAL PROCESSOR is using
the CPU-signaling-and-response facility. The CPU which is concur­
rently executing the instruction
can be any CPU in the configuration
other than this CPU, and the CPU address can be any address, includ­
ing that of this CPU or an invalid
address. The order is rejected. Condition code 2 is set.
2. The addressed CPU is not opera­ tional; that is, it ;s not provided in the installation, it is not in
the configuration, it is in any of
certain customer-engineer test
modes, or its power is off. The
order is rejected. Condition code
3 is set. This condition cannot arise as a result of a SIGNAL PROCESSOR by a CPU addressing
itself.
3. One of the following conditions
exists at the addressed CPU: a. A previously issued start,
stop, restart, or stop-and­
store-status order has been
accepted by the addressed CPU, and execution of the function
requested by the order has not
yet been completed.
b. A manual start, stop, restart,
or store-status function has
been initiated at the addressed CPU, and the function has not
yet been completed. This
condition cannot arise as a
result of a SIGNAL PROCESSOR by a CPU addressing itself.
If the currently specified order is
sense, external call, emergency
signal, start, stop, restart, or
stop and store status, then the 4-40 System/370 Principles of Operation 4.
order is rejected, and condition
code 2 is set. If the currently
specified order is an IMl, one of
the reset orders, or an unassigned
or not-implemented order, the order
code is interpreted as described in
the section "Status Bits" in this
chapter. One of the following conditions
exists at the addressed CPU: a. A previously issued initial­
program-reset, program-reset,
IML, initial-CPU-reset, or CPU-reset order has been
accepted by the addressed CPU, and execution of the function
requested by the order has not
yet been completed.
b. A manual-reset or IML function
has been initiated at the
addressed CPU, and the function
has not yet been completed.
This condition cannot arise as
a result of a SIGNAL PROCESSOR by a CPU addressing itself.
If the currently specified order is
sense, external call, emergency
signal, start, stop, restart, or
stop and store status, then the
order is rejected, and condition
code 2 is set. If the currently
specified order is an IML, one of
the reset orders, or an unassigned
or not-implemented order, either
the order is rejected and condition
code 2 is set or the order code is
interpreted as described in the
section "Status Bits" in this chap­
ter.
When any of the conditions described in
items 3 and 4 exists, the addressed CPU is referred to as "busy." Busy is not
indicated if the addressed CPU is in the
check-stop state or when the operator­
intervening condition exists. A CPU­ busy condition is normally of short
duration; however, the conditions
described in item 3 may last indefinite­
ly because of a string of interruptions,
because of an incomplete READ DIRECT operation, or because of an invalid
address in the prefix register. In this
situation, however, the CPU does not
appear busy to any of the reset orders
or to an IML.
When the conditions described in items 1
and 2 above do not apply and operator­
intervening and receiver-check status
conditions do not exist at the addressed CPU, reset orders may be accepted
regardless of whether the addressed CPU has completed a previously accepted
order. This may cause the previous
order to be lost when it 1S only
partially completed, making unpredict- .• able whether the results defined for the lost order are obtained.