2. The status-modifier bit, in
conjunction with the device-end
bit, has its normal effect during
the IPL I/O operation, causing the
channel to fetch and chain to the
CCW whose address is 16 higher than
that of the current CCW. This
applies also to the initial chain­
ing that occurs after completion of
the read operation specified by the
implicit CCW. 3. The PSW that is loaded at the
completion of the IPL operation may
be provided by the first eight
bytes of the IPL I/O operation or
may be placed at absolute locations 0-7 by a subsequent CCW.
4. When the PSW in absolute location 0 has bit 14 set to one, the CPU is
placed in the wait state after the IPL operation is completed; at that
point, the load and manual indica­
tors are off, and the wait
indicator is on.
5. Activating the load-normal key
implicitly specifies the use of the
first 24 bytes of main storage.
Since the remainder of the IPL program may be placed in any part
of storage, it is possible to
preserve such areas of storage as
may be helpful in debugging and
recovery. When the load-clear key
is activated, the IPL program
starts with a cleared machine in a known state, except that informa­
tion on external storage remains
unchanged. STORE STATUS
The store-status facility includes:
1. A change to the operation of the
system-reset-normal key. With the
store-status facility installed,
activating the system-reset-normal
key causes a CPU-reset operation
and a subsystem-reset operation to
be performed; without this
facility, an initial-CPU-reset operation and subsystem-reset oper­
ation are performed.
2. An operator-initiated store-status
function.
The store-status operation places the
contents of the CPU registers, except
for the TOO clock, in assigned storage
locations.
The figure "Assigned Storage Locations
for Store Status" lists the fields that are stored, their length, and their I location in main storage. CPU timer* Clock comparator*
Current PSWH Prefix* Model-dependent feat.* Fl-pt registers 0-6* General registers 0-15 Control registers 0-15 Explanation:
Length
in
Bytes 8 8 8 4
4
32
64
64
Absolute
Address
216
224
256
264
268
352
384
448 * If the facility is not installed,
the contents of the field in
storage remain unchanged. " In the BC mode, the ILC is unpre­
dictable, and the interruption
code is stored as zeros.
Assigned Storage Locations for Store
Status
In the BC mode, the instruction-length
code in the PSW is unpredictable, and an
interruption code of zero is stored.
The information provided for uninstalled
or unassigned control-register positions
is unpredictable. If the CPU timer,
clock comparator, prefix register or
floating-point facility is not
installed, the contents of the corre­
sponding locations in storage remain
unchanged.
The word beginning at absolute location
268 is reserved for storing additional
status as required by certain model­
dependent facilities. If no facility
requlrlng this location is installed,
the contents of the field remain
unchanged upon execution of the store­
status function.
The contents of the registers are not
changed. If an error is encountered
during the operation, the CPU enters the
check-stop state.
The store-status operation can be initi­ ated manually by use of the store-status
key (see Chapter 12, "Operator Facili­
ties"). The store-status operation can
also be initiated at the addressed CPU by executing SIGNAL PROCESSOR, specify­
ing the stop-and-store-status order. MULTIPROCESSING The multiprocessing facility provides
for the interconnection of CPUs, via a
common main storage, in order to enhance
system availability and to share data
and resources. The multiprocessing
Chapter 4. Control 4-37
facility includes the following facili­ ties: Shared main storage Prefixing CPU-address identification CPU signaling and response TOO-clock synchronization
TOD-clock synchronization is described
earlier in this chapter. Prefixing is
described in Chapter 3, "storage." Shared main storage, CPU-address iden­ tification, and CPU signaling and
response are described in the sections
which follow.
Associated with these facilities are four extensions to the external inter-
ruption (external call, emergency signal, TOD-clock-sync check, and malfunction alert), which are described
in Chapter 6, "Interruptions"; control­
register positions for the TOD-clock­ sync-control bit and for the masks for
the external-interruption conditions,
which are listed in the section "Control
Registers" in this chapter; and the
instructions SET PREFIX, SIGNAL PROCESS­ OR, STORE CPU ADDRESS, and STORE PREFIX, which are described in Chapter 10, "Con­
trol Instructions." Channels in a multiprocessing configura­
tion are connected to a particular CPU. Only that CPU which is connected to a channel can initiate I/O operations at
that channel, and all interruption
conditions are directed to that CPU. When channel-set switching is installed,
the channel-CPU connection can be
changed by means of the program.
SHARED MAIN STORAGE The shared-main-storage facility permits
more than one CPU to have access to
common main-storage locations. All CPUs having access to a common main-storage
location have access to the entire
2K-byte block containing that location
and to the associated storage key. When
the storage-key 4K-byte-block facility
is installed, all CPUs having access to
a common main-storage location have
access to the entire 4K-byte block
containing that location and to the associated single key in that block.
All CPUs and all channels in the config­
uration refer to a shared main-storage location using the same absolute
address.
4-38 System/370 Principles of Operation CPU-ADDRESS IDENTIFICATION Each CPU in a multiprocessing configura­
tion has a number assigned, called its CPU address. A CPU address uniquelY identifies one CPU within a configura­
tion. The CPU is designated by specify­
ing this address in the CPU-address field of SIGNAL PROCESSOR. The CPU signaling a malfunction alert, emergency
signal, or external call is identified
by storing this address in the CPU­ address field with the interruption.
The CPU address is assigned during
system installation and is not changed
as a result of reconfiguration changes.
The program can determine the address of
the CPU by using STORE CPU ADDRESS. CPU SIGNALING AND RESPONSE The CPU-signaling-and-response facility
consists of SIGNAL PROCESSOR and a mech­
anism to interpret and act on several
order codes. The facility provides for
communications among CPUs, including
transmitting, receiving, and decoding a
set of assigned order codes; initiating
the specified operation; and responding
to the signaling CPU. If a CPU has the
CPU-signaling-and-response facility
installed, it can address SIGNAL PROCES­ SOR to itself. SIGNAL PROCESSOR is
described in Chapter 10, "Control
Instructions." SIGNAL-PROCESSOR ORDERS The signal-processor orders are
fied in bit positions 24-31
second-operand address of SIGNAL SOR and are encoded as shown
figure "Encoding of Orders." Code Order 00 Unassigned 01 Sense 02 External call 03 Emergency signal 04 Start 05 Stop 06 Restart 07 Initial program reset 08 Program reset 09 Stop and store status
speci­
of the PROCES­ in the OA Initial microprogram load OB Initial CPU reset DC CPU reset OD-FF Unassigned
Encoding of Orders
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