2. The status-modifier bit, in
conjunction with the device-end
bit, has its normal effect during
theIPL I/O operation, causing the
channel to fetch and chain to the
CCW whose address is 16 higher than
that of the current CCW. This
applies also to the initial chain
ing that occurs after completion of
the read operation specified by the
implicit CCW.3. The PSW that is loaded at the
completion of theIPL operation may
be provided by the first eight
bytes of theIPL I/O operation or
may be placed at absolute locations0-7 by a subsequent CCW.
4. When thePSW in absolute location 0 has bit 14 set to one, the CPU is
placed in the wait state after theIPL operation is completed; at that
point, the load and manual indica
tors are off, and the wait
indicator is on.
5. Activating the load-normal key
implicitly specifies the use of the
first 24 bytes of main storage.
Since the remainder of theIPL program may be placed in any part
of storage, it is possible to
preserve such areas of storage as
may be helpful in debugging and
recovery. When the load-clear key
is activated, theIPL program
starts with a cleared machinein a known state, except that informa
tion on external storage remains
unchanged.STORE STATUS
The store-status facility includes:
1. A change to the operation of the
system-reset-normal key. With the
store-status facility installed,
activating the system-reset-normal
key causesa CPU-reset operation
anda subsystem-reset operation to
be performed; without this
facility, aninitial-CPU-reset operation and subsystem-reset oper
ation are performed.
2. An operator-initiated store-status
function.
The store-status operation places the
contents of theCPU registers, except
for theTOO clock, in assigned storage
locations.
The figure "Assigned Storage Locations
for StoreStatus" lists the fields that are stored, their length, and their I location in main storage. CPU timer* Clock comparator*
CurrentPSWH Prefix* Model-dependent feat.* Fl-pt registers 0-6* General registers 0-15 Control registers 0-15 Explanation:
Length
in
Bytes8 8 8 4
4
32
64
64
Absolute
Address
216
224
256
264
268
352
384
448* If the facility is not installed,
the contents of the field in
storage remain unchanged." In the BC mode, the ILC is unpre
dictable, and the interruption
code is stored as zeros.
Assigned Storage Locations for Store
Status
In the BC mode, the instruction-length
codein the PSW is unpredictable, and an
interruption code of zero is stored.
The information provided for uninstalled
or unassigned control-register positions
is unpredictable. If theCPU timer,
clock comparator, prefix register or
floating-point facility is not
installed, the contents of the corre
sponding locations in storage remain
unchanged.
The word beginning at absolute location
268 is reserved for storing additional
status as required by certain model
dependent facilities. If no facility
requlrlng this location is installed,
the contents of the field remain
unchanged upon execution of the store
status function.
The contents of the registers are not
changed. If an error is encountered
during the operation, theCPU enters the
check-stop state.
The store-status operation can beiniti ated manually by use of the store-status
key (see Chapter 12,"Operator Facili
ties"). The store-status operation can
also be initiated at the addressedCPU by executing SIGNAL PROCESSOR, specify
ing the stop-and-store-status order.MULTIPROCESSING The multiprocessing facility provides
for the interconnection ofCPUs, via a
common main storage, in order to enhance
system availability and to share data
and resources. The multiprocessing
Chapter 4. Control 4-37
conjunction with the device-end
bit, has its normal effect during
the
channel to fetch and chain to the
CCW whose address is 16 higher than
that of the current CCW. This
applies also to the initial chain
ing that occurs after completion of
the read operation specified by the
implicit CCW.
completion of the
be provided by the first eight
bytes of the
may be placed at absolute locations
4. When the
placed in the wait state after the
point, the load and manual indica
tors are off, and the wait
indicator is on.
5. Activating the load-normal key
implicitly specifies the use of the
first 24 bytes of main storage.
Since the remainder of the
of storage, it is possible to
preserve such areas of storage as
may be helpful in debugging and
recovery. When the load-clear key
is activated, the
starts with a cleared machine
tion on external storage remains
unchanged.
The store-status facility includes:
1. A change to the operation of the
system-reset-normal key. With the
store-status facility installed,
activating the system-reset-normal
key causes
and
be performed; without this
facility, an
ation are performed.
2. An operator-initiated store-status
function.
The store-status operation places the
contents of the
for the
locations.
The figure "Assigned Storage Locations
for Store
Current
Length
in
Bytes
4
32
64
64
Absolute
Address
216
224
256
264
268
352
384
448
the contents of the field in
storage remain unchanged.
dictable, and the interruption
code is stored as zeros.
Assigned Storage Locations for Store
Status
In the BC mode, the instruction-length
code
interruption code of zero is stored.
The information provided for uninstalled
or unassigned control-register positions
is unpredictable. If the
clock comparator, prefix register or
floating-point facility is not
installed, the contents of the corre
sponding locations in storage remain
unchanged.
The word beginning at absolute location
268 is reserved for storing additional
status as required by certain model
dependent facilities. If no facility
requlrlng this location is installed,
the contents of the field remain
unchanged upon execution of the store
status function.
The contents of the registers are not
changed. If an error is encountered
during the operation, the
check-stop state.
The store-status operation can be
key (see Chapter 12,
ties"). The store-status operation can
also be initiated at the addressed
ing the stop-and-store-status order.
for the interconnection of
common main storage, in order to enhance
system availability and to share data
and resources. The multiprocessing
Chapter 4. Control 4-37