1. All SIGNAL PROCESSOR orders can be
addressed to this same CPU. The
following are examples of functions
obtained by a CPU addressing SIGNAL PROCESSOR to itself:
a. Sense indicates whether an
external-call condition is pending.
b. External call and emergency signal cause the corresponding
interruption conditions to be
generated. External call can be rejected because of-a-previ­ ously generated external-call
condition.
c. Start sets condition code 0 and
has no other effect.
d. stop causes the
condition code 0, interruptions for
enabled, and enter
state. CPU to set
take pending
which it is
the stopped
e. Restart provides a means to
store the current PSW. f. stop and store status causes
the machine to stop and store
all current status.
2. Two CPUs can simultaneously execute SIGNAL PROCESSOR, with each CPU addressing the other. When this
occurs, one CPU, but not both, can
find the access path busy because of the transmission of the order
code or status bits associated with
SIGNAL PROCESSOR that is being
executed by the other CPU. Alter­
natively, both CPUs can find the access path available and transmit
the order codes to each other. In
particular, two CPUs can simultane­
ously stop, restart, or reset each
other. CHANNEL-SET SWITCHING The channel-set-switching facility
permits a collection of chnnneis to be
switched from one CPU to another. The
collection of channels which are switched as a group is called a channel
set. A CPU can be connected to only one
channel set at a time, and a channel set
can be connected to only one CPU at a
time. The switching operation controls
only the execution of I/O instructions
and I/O interruptions. Other channel
activity, such as chaining and data­
transfer operations, is not controlled
by the switching. When a channel set is switched to a
particular CPU, it is said to be connected to that CPU. Channel-set switching permits any channel set in the configuration to be connected to any CPU in the configuration. However, a chan­
nel set can be connected to no more than
one CPU at a time, and vice versa. When
a channel set is not connected to a CPU, it is said to be disconnected. On a
particular CPU, all I/O instructions
executed address only the channels with­
in the channel set which is currently
connected to that CPU. Initial program
reset and program reset issued to a CPU result in the resetting of the CPU and of only those channels which are
currently connected to that CPU. Simi­ larly, I/O interruptions caused by a
channel which is part of a particular
channel set occur on the CPU to which
the channel set is currently connected. Chaining and data-transfer operations by
the channel continue, independent of
whether the channel set is connected to
a CPU. Channel sets can be connected and disconnected by means of two
instructions, CONNECT CHANNEL SET and DISCONNECT CHANNEL SET, which are defined in Chapter 10, "Control Instructions." These instructions
select a particular channel set by means
of a 16-bit channel-set address. When
the addressed channel set is not opera­
tional, execution of these instructions
results in a setting of condition code
3. A channel set is not operational
when it is not provided in the installa­
tion, its power is off, it is not in the
configuration, or it is in any of certain customer-engineer test modes.
Depending on the model, a channel set may be not operational when all of the
channels in the channel set are not
operational.
When a channel set is connected to a CPU and the CPU becomes not operational, the
channel set may also become not opera­
tional, or it may become disconnected and remain in the configuration. A CPU can become not operational because of certain customer-engineer test modes being SQt, because model-dependent reconfiguration controls remove it from the configuration, or because its power i s off.
The number of CPUs and channel sets in a purticular configuration ;s not neces­ sarily the same.
When system reset normal, system reset clear, load normal, or load clear is activated on any CPU in the configura­ tion, in the absence of any override by
model-dependent reconfiguration controls, then: • All channels within all sets in the configuration system reset, channel perform Chapter 4. Control 4-43

• Each channel set which has a home CPU which is operational and in the configuration is connected to its
home CPU, and • Each channel have a home
tional and in
disconnected.
set which does not CPU which is opera­ the configuration is By definition, the CPU to which a chan­
nel set is connected after subsystem
reset is called the home CPU for that
channel set. The address of the channel
set mayor may not be the same as the address of its home CPU. When no channel set is connected to a particular CPU, the execution of any I/O instruction results in a setting of
4-44 System/370 Principles of Operation condition code 3. When a channel set is
connected to a particular CPU, condition
code 3 to an I/O instruction normally
indicates that the addressed channel, subchannel, or device is not
operational. The I/O instructions are
described in Chapter 13, "Input/Output Operations." The connection or discon­
nection of a channel set is not
considered to be a change in the channel
state for purposes of setting to one the
machine-check external-damage-code bit 3, channel not operational. The setting
of this bit, even when a channel set is disconnected, indicates only those
changes from the operational state to
the not-operational state which would be seen if the channel set were connected
to a CPU.