CHAPTER PROGRAM EXECUTION Instructions •.•••.••••..••••••..•••.••••.....•••.•.•••••.. 5-2 Operands ••••••.••••••.•••.••.••••••.••.••..••••••••••.•. 5-2
Instruction Format •••.•.••••.•••••••••.•.•••••...•.•••.. 5-3
Register Operands ....••••..•.•.•.•••.•...•.•.•••..•••. 5-4 Immediate Operands ..•.••••.•.•..••........••...•.•..•. 5-4
Storage Operands •....•......•••••.••.•..••••••.••••.•. 5-4
Address Generation .••.....•..•..•.••••.•..•••••••.•..••••. 5-5
Sequential Instruction-Address Generation •••.••••••..•.. 5-5
Operand-Address Generation .....•.•.•...••..........•..•. 5-5
Branch-Address Generation •.•.••....•.......•..........•. 5-6
Instruction Execution and Sequencing ••.•...••.•••••..•.••. 5-6 Decision Making ..•.•...•.•••..••.•.•••.•...•••.••..••••. 5-6
Loop Control ......•......•...•.•...•••.•.••.........••.. 5-6
Subroutine Linkage ................•..•.•............•... 5-6
Interruptions ..••.•....•.•...•.•..•••..•...•.•••..•..... 5-8
Types of Instruction Ending .•..•.••.••.•....•.••..•.•.•. 5-8 Completion .•..•.•..••.•..•....••..•..•..•••.•.•.....•. 5-9
Suppression ...•..............•..•................•.•.. 5-9 Nullification ..•••......•..•..•.•••..•.....••......... 5-9
Termination ...••....•....•••.••...•..•...•......•..... 5-9
Interruptible Instructions •.••......••.••..•.••.•....•.. 5-9 Point of Interruption ................••........•....•. 5-9
Execution of Interruptible Instructions ............... 5-9
Exceptions to Nullification and Suppression ••.•....•...• 5-11
Storage Change and Restoration for
OAT-Associated Access Exceptions .•..••...•.••.•.••••. 5-11
Modification of OAT-Table Entries ....•..•.•.........•. 5-12 Trial Execution for Editing Instructions and
TRANSLATE ........•........•.....•..........••.•..•... 5-12
Interlocked Update for Nullification and
Suppression ...................................•...••. 5-12
Dual-Address-Space Control .•..•..............••........... 5-13 Summary .•.....................••.....•.•..........•..... 5-13
DAS Functions .......•...•......•..........•............• 5-14
Using Two Address Spaces ...•..........•..•...•........ 5-14 Changing to Other Spaces ........•.............••...... 5-14
Moving Information .....•......•.......•......•...•.... 5-15
Transferring Program Control •...........••.....•...... 5-15
Handling Storage Keys and the PSW Key •.............•.• 5-16 Program-Problem Analysis .•.............•........•...•. 5-17
DAS Authorization Mechanisms .•...........•..•........•.... 5-17
Mode Requirements •...•...•....••...•................. :5-17 Extraction-Authority Control ...•...•.••......•.••..•.. 5-17 P S l·J - Key Mas k ..................................•....... 5 -18
Secondary-Space Control ............................... 5-18
Subsystem-Linkage Control •...•...••....•.•......•..... 5-18
ASN-Translation Control •.•.........•.............•.... 5-18
Authorization Index .•...•.•.•....•.......•...•........ 5-18 PC-Number Translation ...•..•......•..•.•.•................ 5-21 PC-Number Translation Control .•..•.•....•.••.•.......... 5-21 PC-Number Translation Tables ....•..•.....•..•.•......•.. 5-21
Linkage-Table Entries •.....•.•..•..•.....•......••.... 5-21
Entry-Table Entries ..............•.................... 5-22 PC-Number-Translati on Process ....•...................... 5-22
Linkage-Table lookup ..•...•..••...•..•.••.•.....•..••. 5-23
Entry-Table Lookup ...................•.••..••.•.•.•... 5-24
Recognition of Exceptions during PC-Number Translation ..•......•.•.......•..•.......••.......... 5-24
Sequence of Storage References ..••••.•........•.•••..•.... 5-24
Conceptual Sequence .•....•••..•.••...•....•••••.•••... 5-24 OverlBpped Operation of Instruction Execution ...•.•... 5-24
Divisible Instruction Execution ................•.•.... 5-25
Interlocl<s for Virtual-Storage References ....•....•.•.•. 5-25
Instruction Fetching ..••.•.•....•.•.•.••...••.•••••••.•. 5-26
OAT-Table Fetches .........•.•.•.••.••.....•.•.•.•..••... 5-27
Storage-Key Accesses ..••..•.•...•.•••.•.••••••••.•...... 5-28 Storage-Operand References ..•..•.••.•.••.••.•.•......•.. 5-28 Storage-Operand Fetch ReferencQs •••.•••••••••••••••••• 5-29 Chapter 5. Program Execution 5-1
Storage-Operand Store References •••••••••••••••••••••• 5-29
Storage-Operand Update References ••••••••••••••••••••. 5-29
Storage-Operand Consistency ••••••••••••••••••••••••••••. 5-30 Single-Access References •••••••••••.••••.••••••••••••• 5-30 Multiple-Access References •••••••••••••••••.•••••••••• 5-31 Block-Concurrent References .........•....•.••••••••••• 5-31 Consistency Specification .•.•..••.•.•...•••.•••••••••• 5-31 Relation between Operand Accesses ••••••••••••••••••••••• 5-32 Other Storage References •••.••••.••••••••••••••.•••.•••• 5-33 Serialization •.....•.....•••..•••••.•••.•••.•••••.•••.•••• 5-33 CPU Serialization ••...•••.•...•••.•.••••..••••••.••.•••• 5-33 Channel-Program Serialization ••.•••••••.•••.•••••••.•.•. 5-34
Normally, operation of the CPU is
controlled by instructions in storage
that are executed sequentially, one at a
time, left to right in an ascending
sequence of storage addresses. A change
in the sequential operation may be
caused by branching, LOAD PSW, inter­
ruptions, SIGNAL PROCESSOR orders, or manual intervention. INSTRUCTIONS Each instruction consists of two major
parts: An operation code Cop code), which
specifies the operation to be
performed The designation of the operands
that participate OPERANDS Operands can be grouped in three
classes: operands located in registers,
immediate operands, and operands in
storage. Operands may be either explic­
itly or implicitly designated.
Register operands can be located in
general, floating-point, control
registers, with the type of register
identified by the op code. The register
containing the operand is specified by
identifying the register in a four-bit
field, called the R field, in the
instruction. For some instructions, an operand is located in an implicitly designated register, the register being
implied by the op code. Immediate operands are contained within
the instruction, and the eight-bit field
containing the immediate operand is
called the I field. Operands in storage may have an implied
length; be specifled by a bit mask; be specified by a four-bit or eight-bit
5-2 System/370 Principles of Operation length specification, called the L
field, in the instruction; or have a
length specified by the contents of a
general register. The addresses of
operands in storage are specified by
means of a format that uses the contents
of a general register as part of the
address. This makes it possible to:
1. Specify a complete address by using
an abbreviated notation
2. Perform address manipulation using
instructions which employ general
registers for operands
3. Modify addresses by program means
without alteration of the instruc­
tion stream
4. Operate independent of the location
of data areas by directly using
addresses received from other
programs
The address used to refer to storage either is contained in a register desig­
nated by the R field in the instruction
or is calculated from a base address,
index, and displacement, specified by
the B, X, and D fields, respectively, in
the instruction.
To describe the execution of
instructions, operands are designated as
first and second operands and, in some
cases, third operands.
In general, two operands participate in an instruction execution, and the result
replaces the first operand. However, CONVERT TO DECIMAL, TEST BLOCK, and instructions with "store" in the instruction name (other than STORE THEN
AND SYSTEM MASK and STORE THEN OR SYSTEM MASK) use the second-operand address to
designate a location in which to store.
TEST AND SET, COMPARE AND SWAP, and COMPARE DOUBLE AND SWAP may perform an update on the second operand. Except
when otherwise stated, the contents of
all registers and storage locations
participating in the addressing or
execution part of an operation remain
unchanged.
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