Partial completion of instruction
execution occurs only for interruptible
instructions; it is described in the
section "Interruptible Instructions"
later in this chapter. Completion Completion of instruction execution
provides results as called for in the
definition of the instruction. When an
interruption occurs after the completion
of the execution of an instruction, the
instruction address in the old PSW designates the next sequential instruc­
tion.
Suppression
Suppression of instruction execution
causes the instruction to be executed as if it specified "no operation." The
contents of any result fields, including
the condition code, are not changed.
The instruction address in the old PSW on an interruption after suppression
designates the next sequential instruc­
tion.
Nullification of instruction execution
has the same effect as suppression,
except that when an interruption occurs
after the execution of an instruction
has been nullified, the instruction
address in the old PSW designates the
instruction whose execution was nulli­
fied (or an EXECUTE instruction, as
appropriate) instead of the next sequen­
tial instruction.
Termination
Termination of instruction execution
causes the contents of any fields due to
be changed by the instruction to be
unpredictable. The operation may
replace all, part, or none of the
contents of the designated result fields
and may change the condition code if
such change is called for by the
instruction. Unless the interruption is
caused by a machine-check condition, the
validity of the instruction address in
the PSW, the interruption code, and the ILC are not affected, and the state or
the operation of the machine is not affected in any other way. The instruc­ , tion address in the old PSW on an
interruption after termination desig­
nates the next sequential instruction. INTERRUPTIBLE INSTRUCTIONS Point of Interruption
For most instructions, the entire
execution of an instruction is one oper­
atipn. An interruption is permitted
between operations; that is, an inter­
ruption can occur after the performance
of one operation and before the start of
a subsequent operation.
For the following instructions, referred
to as interruptible instructions, an interruption is permitted after partial
completion of the instruction: COMPARE LOGICAL LONG MOVE LONG TEST BLOCK Interruptible instructions of the
vector facility (see the publi­
cation IBM System/370 Vector
Operations, SA22-712S)
The execution of an interruptible
instruction is considered to consist in
the execution of a number of units of
operation, and an interruption is
permitted between units of operation.
The amount of data processed in a unit
of operation depends on the particular
instruction and may depend on the model
and on the particular condition that
causes the execution of the instruction
to be interrupted.
Whenever points of interruption that
include those occurring within the
execution of an interruptible instruc­
tion are discussed, the term "unit of
operation" is used. For a noninterrup­
tible instruction, the entire execution
consists, in effect, in the execution of
one unit of operation.
When an instruction consists of a number
of units of operation and an inter­
ruption occurs after some, but not all,
units of operation have been completed,
the instruction is said to be partially
completed. In this case, the type of
ending (completion, inhibition, nullifi­
cation, suppression) is associated with
the unit of operation. In the case of
termination, the entire instruction is
terminated, not just the unit of opera­
tion.
Execution of Interruptible Instructions
The execution of an interruptible
instruction is completed when all units
of operation associated with that
instruction are completed. When an
interruption occurs after completion,
inhibition, nullification, or
suppression of a unit of operation, all Chapter 5. Program Execution 5-9

preceding units of operation have been completed, and subsequent units of oper­
ation and instructions have not been
started. The main difference between
these types of ending is the handling of
the current unit of operation and wheth­
er the instruction address stored in the
old PSW identifies the current instruc­
tion or the next sequential instruction.
At the time of an interruption, changes
to register contents, which are due to
be made by an interruptible vector
instruction beyond the point of inter­
ruption, have not yet been made. Chang­ es to storage locations, however, which
are due to be made by an interruptible
vector instruction beyond the point of
interruption, may have occurred for one
or more storage locations beyond the
location containing the element identi­
fied by the interruption parameters, but
not for any location beyond the last
element specified by the instruction and
not for any locations for which access
exceptions exist. Changes to storage
locations or register contents which are due to be made by instructions following
the interrupted instruction have not yet been made at the time of interruption. Completion: On completion of the last
unit of operation of an interruptible
instruction, the instruction address in
the old PSW designates the next sequen­ tial instruction. The result location
for the current unit of operation has been updated. It depends on the partic­
ular instruction how the operand parameters are adjusted. On completion
of a unit of operation other than the
last one, the instruction address in the
old PSW designates the interrupted
instruction or an EXECUTE instruction, as appropriate. The result location for
the current unit of operation has been
updated. The operand parameters are
adjusted such that the execution of the
interrupted instruction is resumed from
the point of interruption when the old PSW stored during the interruption is
made the current psw.
Inhibition:
inhibited,
When a unit of operation is
the instruction address in 5-10 System/370 Principles of Operation the old PSW designates the interrupted
instruction or an EXECUTE instruction,
as appropriate. The result location for
the current unit of operation is not
changed. The operand parameters are
adjusted such that, if the instruction
is reexecuted, execution of the inter­
rupted instruction is resumed with the
next unit of operation. Inhibition
occurs only during interruptible vector
instructions and is described in more
detail in the publication IBM System/370 Vector Operations, SA22-7125.
Nullification: When a unit of operation
is nullified, the instruction address in
the old PSW designates the interrupted
instruction or an EXECUTE instruction,
as appropriate. The result location for
the current unit of operation remains
unchanged. The operand parameters are
adjusted such that, if the instruction
is reexecuted, execution of the inter­
rupted instruction is resumed with the
current unit of operation.
Suppression: When a unit of operation
is suppressed, the instruction address
in the old PSW designates the next
sequential instruction. The operand
parameters, however, are adjusted so as
to indicate the extent to which instruc­
tion execution has been completed. If
the instruction is reexecuted after the
conditions causing the suppression have
been removed, the execution is resumed
with the current unit of operation.
Termination: When an exception which
causes termination occurs as part of a
unit of operation of an interruptible
instruction, the entire operation is terminated, and the contents, in
general, of any fields due to be changed
by the instruction are unpredictable. On such an interruption, the instruction
address in the old PSW designates the
next sequential instruction.
The differences among the five types of
ending for a unit of operation are
summarized in the figure "Types of
Ending for a Unit of Operation."