Unit of Operation Is
Instruction
Address Operand Parameters
Current Result
Location
Completed
Last unit of
operation
Any other unit
of operation
Next instruc­
tion
Current in­
struction
Depends on the
instruction
Next unit of
operation
Changed
Changed
Inhibited Current in­
struction
Next unit of
operation
Unchanged
Nullified Current in­
struction
Current unit
of operation
Unchanged
Suppressed Next instruc­
tion
Current unit
of operation
Unchanged
Terminated Next instruc­
tion
Unpredictable Unpredictable
Types of Ending for a Unit of Operation Programming Notes
1. Any interruption, other than super­
visor call and some program inter­
ruptions, can occur after a partial
execution of an interruptible
instruction. In particular, inter
ruptions for external, I/O, machine-check, restart, and program
interruptions for access and PER events can occur units of operation.
2. The amount of data processed in a
unit of operation of an interrupti­
ble instruction depends on the
model and may depend on the type of
condition which causes the
execution of the instruction to be
interrupted or stopped. Thus, when
an interruption occurs at the end
of the current unit of operation,
the length of the unit of operation
may be different for different
types of interruptions. Also, when
the stop function is requested
during the execution of an inter­
ruptible instruction, the CPU enters the stopped state at the
completion of the execution of the
current unit of operation. Simi­
larly, in the instruction-step
mode, only a single unit of opera­
tion is performed, but the unit of
operation for the various cases of
stopping may be different. EXCEPTIONS TO NULLIFICATION AND SUPPRESSION In certain unusual situations, the
result fields of an instruction having a
store-type operand are changed in spite
of the occurrence of an exception which
would normally result in nullification
or suppreSSlon. These situations are
exceptions to the general rule that the
operation is treated as a no-operation
when an exception requiring nullifica­
tion or suppression is recognized. Each
of these situations may result in the
turning on of the change bit associated
with the store-type operand, even though
the final result in storage may appear
unchanged. Depending on the particular
situation, additional effects may be
observable. The extent of these effects
is described along with each of the
situations.
All of these situations are limited to
the extent that a store access does not
occur and the change bit is not set when
the store access is prohibited. For the CPU, a store access is prohibited when­
ever an access exception exists for that
access, or whenever an exception exists
which is of higher priority than the
priority of an access exception for that
access.
When, in these situations, an inter­
ruption for an exception requiring
suppression occurs, the instruction
address in the old PSW designates the
next sequential instruction. When an
interruption for an exception requiring
nullification occurs, the instruction
address in the old PSW designates the
instruction causing the exception even
though partial results may have been
stored.
Storage Change and Restoration for
OAT-Associated ACCess Exception-s--
In this section, the term "DAT­
associated access exceptions" is used to
refer to those exceptions which may
Chapter 5. Program Execution 5-11

occur as part of the dynamic-address­
translation process. These exceptions
are page translation, segment trans­
lation, translation specification, and
addressing due to a OAT-table entry
being designated at a location that is not available in the configuration. The first two of these exceptions normally
cause nullification, and the last two
normally cause suppression. Protection
exceptions, including those due to
segment protection, are not considered
to be OAT-associated access exceptions.
For OAT-associated access exceptions, on
some models, channels may observe the effects on storage as described in the following case.
When, for an instruction having a store-type operand, a OAT-associated
access exception is recognized for any
operand of the instruction, that
portion, if any, of the store-type oper­
and which would not cause an exception
may be changed to an intermediate value
but is then restored to the original
value.
The accesses associated with storage
change and restoration for DAT­
associated access exceptions are only
observable by channels and are not
observable by other CPUs in a multiproc­
essing configuration. Except for
instructions which are defined to have
multiple-access operands, the intermedi­
ate value, if any, is always equal to
what would have been the final value if
the OAT-associated access exception had
not occurred.
1. Storage change and restoration for
OAT-associated access exceptions
occur in two main situations:
a. The exception is recognized for
a portion of a store-type oper­
and which crosses a page bound­
ary, and the other portion has
no access exception.
b. The exception is recognized for
one operand of an instruction
having two storage operands
(for example, an SS-format instruction or MOVE LONG), and
the other operand, which is a store-type operand, has no
access exception.
2. To avoid letting a channel observe
intermediate operand values due to
storage change and restoration for
OAT-associated access exceptions
(especially when a CCW chain is
modified), the CPU program should
do one of the following:
5-12 System/370 Principles of Operation • Operate on one storage page at
a time • Perform preliminary testing to
ensure that no exceptions occur
for any of the required pages • Operate with OAT off
Modification of OAT-Table Entries
When a valid and attached OAT-table
entry is chang'ed to a value whi ch would cause an exception, and when, before the TLB is cleared of entries which qualify
for substitution for that entry, an attempt is made to refer to storage by
using a virtual address requiring that
entry for translation, the contents of
any fields due to be changed by the instruction are unpredictable. Results,
if any, associated with the virtual
address whose OAT-table entry was
changed may be placed in those real locations originally associated with the address. Furthermore, it is unpredict­
able whether or not an interruption
occurs for an access exception that was
not initially applicable. On some
machines, this situation may be reported
by means of an instruction-processing­
damage machine check with the delayed­
access-exception bit also indicated. Trial Execution for Editing Instructions
and TRANSLATE
For the instructions EDIT, EDIT AND MARK, and TRANSLATE, the portions of the
operands that are actually used in the operation may be established in a trial
execution for operand accessibility that
is performed before the execution of the instruction is started. This trial execution consists in an execution of the instruction in which results are not
stored. If the first operand of TRANS­ LATE or either operand of EDIT or EDIT AND MARK is changed by another CPU or by a channel, after the initial trial
execution but before completion of
execution, the contents of any fields
due to be changed by the instruction are unpredictable. Furthermore, it is
unpredictable whether or not an inter­
ruption occurs for an access exception
that was not initiallY applicable.
Interlocked Update for Nullification and
Suppression
When an exception which is defined to
cause suppression or nullification is
recognized for an instruction with a
store-type operand, an interlocked-