CRS linkage Table R I ETL
(x64) -} Entry Table R
AKM IA
R: Address is real PC-Humber Translation
linkage-Table Lookup
The linkage-index (LX) portion of the PC number, in conjunction with the
linkage-table origin, is used to select an entry from the linkage table.
The 24-bit real address of the linkage­ table entry is obtained by appending
seven zeros on the r;·ght to the contents
of bit positions 8-24 of control regis­ ter 5 and adding the linkage index, with
two rightmost and 10 leftmost zeros
appended. A carry, if any, into bit
position 7 is ignored. With extended
real addressing, this 24-bit real address is extended on the left with zeros; thus, the linkage table can wrap
from 224 - 1 to zero.
As part of the linkage-table-lookup
process, the leftmost seven bits of the linkage index are compared against the linkage-table length, bits 25-31 of
control register 5, to establish whether the addressed entry is within the link­ age table. If the value in the PC Number P PARM /11//111 linkage-table-length field is less than
the value in the seven leftmost bits of
the linkage index, an LX-translation
exception is recognized.
All four bytes of the linkage-table
entry appear to be fetched concurrently as observed by other CPUs. The fetch
access ;5 not subject to protection.
When the storage address which is gener­ ated for fetching the linkage-table
entry designates a location which is not available in the configuration, an addressing exception is recognized, and the operation is suppressed. Bit 0 of the linkage-table entry speci­
fies whether the entry table correspond­
ing to the linkage index is available.
This bit is inspected, and, if it is one, an lX-translation exception is
recognized.
When no exceptions are recognized in the
process of linkage-table lookup, the
entry fetched .from the I; nkage table
designates the origin and length of the
corresponding entry table. Chapter 5. Program Execution 5-23

Entry-Table lookup
The entry-index (EX) portion of the PC number, in conjunction with the entry­
table origin contained in the linkage­
table entry, is used to select an entry
from the entry table.
The 24-bit real address of the entry­
table entry is obtained by appending six
zeros on the right to the entry-table
origin and adding the entry index, with
four rightmost and 12 leftmost zeros
appended. A carry, if any, into bit
position 7 is ignored. With extended
real addressing, this 24-bit real
address is extended on the left with
zeros. Thus, the entry table can wrap
from 224 - 1 to zero.
As part of the entry-table-lookup proc­ ess, the six leftmost bits of the entry
index are compared against the entry­
table length, bits 26-31 of the
linkage-table entry, to establish wheth­
er the addressed entry is within the table. If the value in the entry-table
length field is less than the value in the six leftmost bits of the entry
index, an EX-translation exception is
recognized.
The 16-byte entry-table entry is fetched
by using the real address. The entry
appears to be fetched word-concurrent as
observed by other CPUs, with the left­
most word fetched first. The order in which the remaining three words are fetched is unpredictable. The fetch
access is not subject to protection.
When the storage address which is gener­ ated for fetching the entry-table entry
designates a location which is not
available in the configuration, an
addressing exception is recognized, and
the operation is suppressed.
The use that is made of the information
fetched from the entry-table entry is
described in the definition of the PROGRAM CALL instruction.
Recogn it i Ot1 of Except ions dur i ng PC-Number Translation
The exceptions which can be encountered
during the PC-number-translation process
and their priority are described in the
definition of the PROGRAM CALL instruc­
tion. SEQUENCE OF STORAGE REFERENCES The following sections describe the
effects of overlapped operation and of
piecemeal execution of a CPU program as that execution is observed in storage.
5-24 System/370 Principles of Operation
Except for the section "Interlocks for
Virtual-Storage References," the effects
described in these sections are observa­
ble only when two or more CPUs or
channels are in simultaneous execution
and access common storage locations.
Thus, in most cases, the program must
take into account the effects which are
described in these sections only for
those cases in which the program inter­
acts with another CPU or a channel. Conceptual Sequence Conceptually, the CPU processes
instructions one at a time, with the
execution of one instruction preceding
the execution of the following instruc­
tion. The execution of the instruction
designated by a successful branch
follows the execution of the branch.
Similarly, an interruption takes place between instructions or, for interrupti­
ble instructions, between units of
operation of such instructions.
The sequence of events implied by the
processing just described is sometimes
called the conceptual sequence. Over.'lilP.ped Operation of Instruction
Execution
Each operation of instruction execution
appears to the program itself to be
performed sequentially, with the current
instruction being fetched after the
preceding operation is completed and
before the execution of the current
operation is begun. This appearance is
maintained even though the storage­
implementation characteristics and
overlap of instruction execution with storage accessing may cause actual proc­ essing to be different. The results generated are those that would have been obtained had the operations been
performed in the conceptual sequence.
Thus, it is possible for an instruction
to modify the next succeeding instruc­ ti on in sto rage. HmoJever, ; n certa in situations involving dynamic address
translation, where different virtual
addresses map to the same real address.
the copies of prefetched instructions
are not necessarily changed. Also, when
a vector-facility instruction is
executed that causes storing into a location from which subsequent
instructions have been prefetched, the copies of the prefetched instructions
are not necessarily changed. In simple models in which operations are
not overlapped, the conceptual and actu­
al sequences are essentially the same.
However, in more complex machines, over­ lapped operation, buffering of operands