and results, and execution times which
are comparable to the propagation delays
between units can cause the actual
sequence to differ considerablY from the
conceptual sequence. In these machines,
special circuitry is employed to detect
dependencies between operations and
ensure that the results obtained, as
observed by the CPU which generates
them, are those that would have been
obtained if the operations had been
performed in the conceptual sequence.
However, other CPUs and channels may,
unless otherwise constrained, observe a
sequence that differs from the conceptu­
al sequence.
Divisible Instruction Execution
It can normally be assumed that the
execution of each instruction occurs as
an indivisible event. However, in actu­
al operation, the execution of an
instruction consists in a series of
discrete steps. Depending on the instruction, operands may be fetched and
stored in a piecemeal fashion, and some
delay may occur between fetching oper­
ands and storing results. As a
consequence, intermediate or partially
completed results may be observable by
other CPUs and by channels. When a program interacts with the opera­
tion on another CPU or a channel, the
program may have to take into consider­
ation that a single operation may
consist in a series of storage refer­
ences, that a storage reference may in
turn consist in a series of accesses,
and that the conceptual and observed
sequences of these accesses may differ.
storage references associated with
instruction execution are of the follow­
ing types: instruction fetches, DAT­
table fetches, and storage-operand
references. For the purpose of describ­
ing the sequence of storage references, acceSSes to storage in order to perform ASH translation, PC-number translation,
and tracing are considered to be
storage-operand references.
Programming Note The sequence of execution of a CPU may
differ from the simple conceptual defi­
nition in the following ways: • As observed by the CPU itself,
instructions may appear to be
prefetched when different effective addresses are used. (See the
section "Interlocks for Virtual­ Storage References" in this
chapter.) • • As observed by other CPUs and by
channels, the execution of an
instruction may appear to be
performed as a sequence of piece­
meal steps. This is described for each type of storage reference in
the following sections.
As observed by other CPUs and by
channels, the storage-operand
accesses associated with one
instruction are not necessarily
performed in the conceptual se­
quence. (See the section "Relation
between Operand Accesses" in this
chapter.) • As observed by channels, in certain
unusual situations, the contents of
storage may appear to change and
then be restored to the original
value. (See the section "Storage Change and Restoration for DAT­
Associated Access Exceptions" in
this chapter.)
INTERLOCKS FOR VIRTUAL-STORAGE REFER­ ENCES As described in the previous section, CPU operation appears to be performed
sequentially as observed by the CPU itself; the results stored by one
instruction appear to be completed
before the next instruction is fetched.
This appearance is maintained in over­
lapped machines by means of special
circuitry to detect accesses to a common
location by comparing effective
addresses.
For purposes of this definition, the
term "effective address" is used to
denote the address before translation,
if any, regardless of whether the
address is virtual, real, or absolute.
If two effective addresses have the same
value, the effective addresses are said
to be the same even though one may be
real or in a different address space.
When all accesses to a main-storage
location are made by using the same
effective address, then the above rule
appears to be strictly maintained, as
observed by the CPU itself. When
different effective addresses are used
to access the common location, the above
rule does not hold in two cases:
1. For some instructions, the defi­
nition specifies the results which
must be obtained for overlapping
operands. This definition is spec­ ified in terms of the sequence of
the storage accesses; that is, the
results of some or all of the
stores of one operand must be
placed in storage before some parts
or all parts of the other operand
are fetched. When the store and
Chapter 5. Program Execution 5-25

2.
the fetch are performed by means of
different effective addresses, then
the operand may appear to be
fetched before the store.
When an instruction changes the
contents of a main-storage location
from which a conceptually subse­
quent instruction is to be
executed, either directly or by
means of EXECUTE, and when differ­
ent effective addresses are used to
designate that location for storing
the result and fetching the
instruction, the instruction may
appear to be fetched before the
store occurs. This does not occur
if an intervening operation causes
the prefetched instructions to be
discarded. A definition of when
prefetched instructions must be
discarded is included in the
section "Instruction Fetching" in
this chapter.
Any change to the storage key appears to
be completed before the conceptually
following reference to the associated
storage block is made, regardless of
whether the reference to the storage
location is made by a virtual, real, or
absolute address. Analogously, any
conceptually prior references to the
storage block appear to be completed
when the key for that block is changed
or inspected. Programming Note A single main-storage location can be
accessed by more than one address in several ways:
1. The OAT tables may be set up such
that multiple addresses in a single
address space, or virtual addresses
in different address spaces, map to
a single real address.
2. The translation of logical,
instruction, and virtual addresses
may be changed by loading the OAT parameters in the control
regi sters, by changi ng the
address-space-control bit in the PSW, or, for logical and instruc­ tion addresses, by turning DAT on
or off.
3. Certain instructions use real
addresses, and the instructions MOVE TO PRIMARY and MOVE TO SECOND­ ARY access two address spaces.
4. Accesses to storage for the purpose
of storing and fetching information
for interruptions is performed by
means of real addresses, and, for
the store-status function, by means
of absolute addresses, whereas
5-26 System/370 Principles of Operation 5.
6.
7 • 8.
accesses by the program may be by
means of virtual addresses.
The real-to-absolute mapping may be
changed by means of the SET PREFIX instruction or a reset.
A main-storage location may be
accessed by channels by means of an
absolute address and by the CPU by
means of a real or a virtual
address.
A main-storage location
accessed by another CPU by
one type of address and by
by means of a different
address.
may be
means of
this CPU type of
The CPU updates the interval timer
by means of a real address, and the
program may access the location by
means of a virtual address.
The primary purpose of this section is
to describe the effects caused in case 1
above.
For case 2, no effect is observable
because prefetched instructions are
discarded when the translation parame­
ters are changed and the delay of stores
by a CPU is not observable by the CPU itself.
For case 3, for those instructions which
fetch by using real addresses (for exam­
ple, LOAD REAL ADDRESS), no effect is
observable because only operand accesses
between instructions are involved. All
instructions that store by using a real
address or that store into another
address space cause pre fetched
instructions to be discarded, and no effect is observable.
Cases 4 and 5 are situations which are
defined to cause serialization, with the
result that prefetched instructions are
discarded. In these cases, no effect is
observable.
The handling of cases 6 and 7 involves
accesses as observed by other CPUs and
by channels and is covered in the
following sections in this chapter.
For case 8, the effect of updating the
interval timer is observable only if an
instruction is fetched from real
location 80 or 82 by using a virtual
address which is not 80 or 82, respec­
tively. INSTRUCTION FETCHING
Instruction fetching consists in fetch­ ing the one, two, or three halfwords
designated by the instruction address in
the current PSW. The immediate field of
an instruction is accessed as part of an