instruction fetch. If, however, an
instruction designates a storage operand
at the location occupied by the instruc­
tion itself, the location is accessed
both as an instruction and as a storage
operand. The fetch of the target
instruction of EXECUTE is considered to be an instruction fetch. The bytes of an instruction may be
fetched piecemeal and are not necessar­
ilyaccessed in a left-to-right direc­
tion. The instruction may be fetched
multiple times for a single execution;
for example, it may be fetched for test­
ing the addressability of operands or
for inspection of PER events, and it may be refetched for actual execution.
Instructions are not necessarily fetched
in the sequence in which they are conceptually executed and are not neces­
sarily fetched each time they are executed. In particular, the fetching
of an instruction may precede the storage-operand references for an
instruction that is conceptually
earlier. The instruction fetch occurs
prior to all storage-operand references for all instructions that are conceptu­
ally later.
An instruction may be prefetched by
using a virtual address only when the associated OAT table entries are attached and valid or when entries which
qualify for substitution for the table entries exist in the TLB. An instruc­
tion that has been prefetched may be interpreted for execution only for the
same virtual address for which the instruction was prefetched. No limit is established on the number of
instructions which may be prefetched, and multiple copies of the contents of a
single storage location may be fetched.
As a result, the instruction executed is
not necessarily the most recently
fetched copy. Storing caused by other CPUs and by channels does not necessar­
ily change the copy of prefetched
instructions. However, if a store that
is conceptually earlier is made by the same CPU using the same effective
address as that by which the instruction
is subsequently fetched, the updated
information is obtained.
All copies of prefetched instructions
are discarded when: • • • • A serializing function is
performed.
The CPU enters the operating state. The CPU changes from OAT on to OAT off or from OAT off to OAT on.
A change is made to
parameter in control
1 when OAT is on.
a translation
register 0 or • • DAS is installed and the CPU chang­ es from one to the other of the
primary-space mode and secondary­
space mode. DAS is installed, and a change is
made to a translation parameter in
control register 7 when OAT is on.
Programming Notes
1. As observed by a CPU i tsel f, its
own instruction prefetching is not
normally apparent; the only excep­
tion occurs when multiple virtual
addresses in a single address
space, or virtual addresses in
different address spaces, map to a single real address. This is
described in the section "Inter­
locks for Virtual-Storage
References" in this chapter.
2. The following are some effects of
instruction prefetching on one CPU as observed by other CPUs and by
channels.
It is possible for one CPU to
prefetch the contents of a storage
location, after which another CPU or a channel can change the
contents of that storage location
and then set a flag to indicate
that the change has been made.
Subsequently, the first CPU can test and find the flag set, branch
to the modified location, and execute the original prefetched
contents.
It is possible, if another CPU or a channel concurrently modifies the
instruction, for one CPU to recog­
nize the changes to some but not
all bit positions of an
instruction.
It is possible for one CPU to
prefetch an instruction and subse­
quently, before the instruction is executed, for another CPU to change
the storage key. As a result, the
first CPU may appear to execute
instructions from a protected stor­
age location. However, the copy of the instructions executed is the
copy prefetched before the location
was protected.
OAT-TABLE FETCHES
The fetching of dynamic-address­
translation (OAT) table entries may
occur as follows:
1. A OAT-table entry may be prefetched
into the translation-Iookaside
Chapter 5. Program Execution 5-27

buffer (TLS) and used from the TLS without refetching from storage,
until the entry is cleared by an
INVALIDATE PAGE TABLE ENTRY, PURGE TLS, or SET PREFIX instruction or
by CPU reset. DAT-table entries are not necessarily fetched in the
sequence conceptually called for;
they may be fetched at any time
they are attached and valid,
including during the execution of
conceptually previous instructions.
2. All bytes of a DAT-table entry
appear to be fetched concurrently,
as observed by other CPUs.
However, the reference to the entry may appear to access a single byte
at a time, as observed by channels.
3. A DAT-table entry may be fetched
even after some operand references
for the instruction have already
occurred. The fetch may occur as
late as just prior to the actual
byte access requiring the DAT-table
entry.
4. A DAT-table entry may be fetched
for each use of the address,
including any trial execution, and
for each reference to each byte of
each operand.
5. The DAT page-table-entry fetch
precedes the reference to the page. When no copy of the page-table entry is in the TlB, the fetch of
the associated segment-table entry
precedes the fetch of the page­ table entry. STORAGE-KEY ACCESSES References to the storage
handled as follows:
key are
1. Whenever a reference to storage is
made and key-controlled protection
applies to the reference, the four
access-control bits and the fetch­
protection bit associated with the
storage location are inspected
concurrently with the reference to
the storage location.
2. When storing is performed, the
change bit is set in the associated
storage key concurrently with the
store operation.
3. The instructions SET STORAGE KEY and SET STORAGE KEY EXTENDED cause
all seven bits to be set concur­
rently in the storage key. The
access to the storage key for SET STORAGE KEY and SET STORAGE KEY EXTENDED follows the sequence rules
for storage-operand store refer­
ences and is a single-access
reference. For SET STORAGE KEY 5-28 System/370 Principles of Operation EXTENDED, the two keys in a double-key 4K-byte block are not
necessarily accessed concurrently.
4. The instructions INSERT STORAGE KEY and INSERT STORAGE KEY EXTENDED provide a consistent image of bits 0-6 of the storage key. Similarly, the instructions INSERT VIRTUAL STORAGE KEY and TEST PROTECTION provide a consistent image of bits 0-4 of the storage key. The access
to the storage key for all of these
instructions follows the sequence
rules for storage-operand fetch
references and is a single-access
reference. For INSERT STORAGE KEY EXTENDED, the two keys in a
double-key 4K-byte block are not
necessarily accessed concurrently.
5. The instructions RESET REFERENCE
BIT and RESET REFERENCE BIT
EXTENDED modify only the reference
bit. All other bits of the storage
key remain unchanged. The refer­
ence bit and change bit are
examined concurrently to set the
condition code. The access to the
storage key for RESET REFERENCE BIT
and RESET REFERENCE BIT EXTENDED
follows the sequence rules for
storage-operand update references.
The reference bit is the only bit which is updated. For RESET REFER­
ENCE BIT EXTENDED, the two keys in
a double-key 4K-byte block are not
necessarily accessed concurrently.
The record of references provided by the
reference bit is not necessarilyaccu­
rate, and the handling of the reference
bit is not subject to the concurrency
rules. However, in the majority of
situations, reference recording approxi­
mately coincides with the storage
reference.
The change bit may be set in cases when
no storing has occurred. See the section "Exceptions to Nullification and Suppression" in this chapter. STORAGE-OPERAND REFERENCES A storage-operand reference is the
fetching or storing of the explicit
operand or operands in the storage
locations designated by the instruction.
During the execution of an instruction,
all or some of the storage operands for
that instruction may be fetched, inter­
mediate results may be maintained for
subsequent modification, and final
results may be temporarily held prior to
placing them in storage. Stores caused
by other CPUs and by channels do not
necessarily affect these intermediate
results.