Explanation:
Locations for the old PSWs, new PSWs, and interruption codes are real locations.
1 A model-independent machine-check interruption code of 64 bits is stored at
real locations 232-239. In the BC mode, the contents of real locations 50-51 are unpredictable.
2 The effect of the machine-check condition is indicated by bits in the machine­
check-interruption code. The setting of these bits indicates the extent of
the damage and whether the unit of operation is nullified, terminated, or
unaffected.
3 The interruption code in the column labeled "Hex" is the hex code for the
basic interruption; this code does not show the effects of concurrent inter­
ruption conditions represented bye, n, p, or x in the column labeled "Binary." 4 Vector-operation and unnormalized-operand exceptions are associated with
the vector facility. "Inhibited" is a type of ending which occurs only for
instructions associated with the vector facility. These are described in
the publication IBM System/370 Vector Operations, SA22-7125. 5 When the interruption code indicates a PER event, an ILC of 0 may be stored
only when bits 8-15 of the interruption code are 10000110 (PER, specifi­
cation).
6 The unit of operation is completed, unless a program exception concurrently
indicated causes the unit of operation to be inhibited, nullified, suppressed,
or terminated.
7 For channels 0-5, channel masks in control register 2 have no effect in the
BC mode. s Bits 16-31 in the old PSW in the BC mode are set to zeros. No interruption
code is provided in the EC mode.
+ Plus the following bits in the control register. One mask bit is provided for
each installed channel; the bit position matches the channel address. * In the BC mode, PER is disabled. Additional masks in control register 9, bit positions 16-31, provide detailed
control over the source of PER general-register-alteration events which are masked by control register 9, bit 3.
c Channel-address bits.
d Device-address bits.
e If one, the bit indicates another concurrent external-interruption condition.
n A possible nonzero code, indicating another concurrent program-interruption
condition.
p If one, the bit indicates a concurrent PER-event interruption condition.
s Bits of the I field of SUPERVISOR CALL.
u Unpredictable in the BC mode; not stored in the EC mode.
x Exception-extension code. This field is described in the publication IBM System/370 Vector Operations, SA22-7125. This field is set to zero except by
vector instructions.
Interruption Action (Part 3 of 3) INTERRUPTION CODE The six classes of interruptions
(external, I/O, machine check, program,
restart, and supervisor call) are
distinguished by the storage locations
at which the old PSW is stored and from
which the new PSW is fetched. For most
classes, the causes are further identi­
fied by an interruption code and, for
some classes, by additional information
placed in permanently assigned real
storage locations during the inter­
ruption. (See also the section "Assigned Storage Locations" in Chapter
3, "Storage.") For external, I/O, program, and supervisor-call inter-
ruptions, the interruption code consists of 16 bits. In the BC mode, the inter­ al ruption code is zero in the PSW stored '1 by the store-status function and is 1 unpredictable when the PSW is displayed.
For external interruptions in the EC
mode, the interruption code is stored at
real locations 134-135. In the BC mode,
the interruption code is placed in the
old PSW. A parameter may be stored at
real locations 128-131, or a CPU address
may be stored at real locations 132-133.
For I/O interruptions in the EC mode,
the interruption code, which contains
the I/O address, is stored at real
locations 186-187. In the BC mode, the
interruption code is placed in the old PSW. Additional information is provided
by the contents of the channel-status
word (CSW) stored at real location 64.
Further information may be provided by
the limited channel logout stored at
real locations 176-179 and by a full
channel logout stored in the fixed­
logout area (real locations 256-351) or
in the I/O-extended-Iogout area.
Chapter 6. Interruptions 6-5
For machine-check interruptions, the
interruption code consists of 64 bits
and is stored at real locations 232-239.
Additional information for identifying
the cause of the interruption and for
recovering the state of the machine may
be provided by the contents of the
machine-check failing-storage address,
the external-damage code, the region
code, and the contents of the fixed­ logout, extended-logout, and machine­
check-save areas. (See Chapter 11, ne-Check Handl i ng. n)
For program interruptions in the EC
mode, the interruption code is stored at
real locations 142-143, and the
instruction-length code is stored in bit
positions 5 and 6 of real location 141.
In the BC mode, the interruption code
and instruction-length code are placed
in the old PSW. Further information may
be provided in the form of the
translation-exception identification,
monitor-class number, monitor code, PER code, and PER address, which are stored at real locations 144-159.
For restart interruptions in the EC
mode, no interruption code is stored.
In the BC mode, an interruption code of
zero is placed in the old PSW. For supervisor-call interruptions in the
EC mode, the interruption code is stored at real locations 138-139, and the
instruction-length code is stored in bit
positions 5 and 6 of real location 137.
In the BC mode, the interruption code
and instruction-length code are placed in the old PSW. ENABLING AND DISABLING
By means of mask bits in the current PSW and in control registers, the CPU may be enabled or disabled for all external, I/O, and machine-check interruptions and
for some program interruptions. When a mask bit is one, the CPU is enabled for
the corresponding class of
interruptions, and these interruptions
can occur.
When a mask bit is zero, the CPU is
disabled for the corresponding inter­
ruptions. The conditions that cause I/O interruptions remain pending.
External-interruption conditions either remain pending or persist until the
cause is removed. Machine-check­
interruption conditions, depending on
the type, are ignored, remain pending,
or cause the CPU to enter the check-stop
state. The disallowed program­
interruption conditions are ignored,
except that some causes are indicated
also by the setting of the condition
code. The setting of the significance
6-6 System/370 Principles of Operation and exponent-underflow program-mask bits
affects the manner in which floating­
point operations are completed when the
corresponding condition occurs.
The CPU is always enabled for program
interruptions for which mask bits are
not provided, as well as the
supervisor-call and restart inter-
ruptions.
The mask bits may allow or disallow all
interruptions within the class, or they
may selectively allow or disallow inter­ ruptions for particular causes. This
control may be provided by mask bits in the PSW that are assigned to particular
causes, such as the bits assigned to the
four maskable program-interruption
conditions. Alternatively, there may be
a hierarchy of masks, where a mask bit in the PSW controls all interruptions within a type, and mask bits in a control register provide more detailed control over the sources.
When the mask bit is one, the CPU is
enabled for the corresponding interrup­
tions. When the mask bit is zero, these
interruptions are disallowed. Interrup­
tions that are controlled by a hierarchy
of masks are allowed only when all
controlling mask bits are ones. Programming Notes
1. Mask bits in the PSW provide a
means of disallowing all maskable
interruptions; thus, subsequent
interruptions can be disallowed by
the new PSW introduced by an inter­
ruption. Furthermore, the mask
bits can be used to establish a
hierarchy of interruption priori­
ties, where a condition in one
class can interrupt the program
handling a condition in another class but not vice versa. To
prevent an interruption-handling
routine from being interrupted
before the necessary housekeeping
steps are performed, the new PSW must disable the CPU for further
interruptions within the same class
or within a class of lower
priority.
2. Because the mask bits in control
registers are not changed as part
of the interruption procedure,
these masks cannot be used to
prevent an interruption immediately
after a previous interruption in
the same class. The mask bits in
control registers provide a means
for selectively enabling the CPU for some sources and disabling it for others within the same class.
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