HANDLING OF FLOATING INTERRUPTION CONDI­ TIONS An interruption condition which can be
presented to any CPU in the configura­
tion is called a floating interruption
condition. The condition is presented
to the first CPU in the configuration
which is enabled for the corresponding
interruption and which can accept the
interruption, and then the condition is cleared and not presented to any other CPU in the configuration. A CPU cannot
accept the interruption when it is in the check-stop state, has an invalid
prefix, is in a string of program inter­
ruptions due to a specification
exception of the type which is recog­ nized early, is executing a READ DIRECT
instruction, or is in the stopped state.
However, a CPU with the rate control set
to instruction step can accept the
interruption when the start key is acti­
vated.
Service signal and certain machine-check
conditions are floating interruption
conditions.
INSTRUCTION-LENGTH CODE The instruction-length code (ILC) occu­
pies two bit positions and provides the
length of the last instruction executed.
It permits identifying the instruction
causing the interruption when the
instruction address in the old PSW designates the next sequential instruc­
tion. The ILC is provided also by the
BRANCH AND LINK instructions. When the old PSW specifies the EC mode,
the ILC for program and supervisor-call
interruptions is stored in bit positions
5 and 6 of the bytes at real locations
141 and 137, respectively. For
external, I/O, machine-check, and
restart interruptions, the ILC is not
stored since it cannot be related to the
length of the last-executed instruction. When the old PSW specifies the BC mode,
the ILC is stored in bit positions 32
and 33 of that PSW. The ILC is meaning­
ful, however, only after a supervisor-
call or program interruption. For
machine-check, external, I/O, and
restart interruptions, the ILC does not
indicate the length of the last-executed
instruction and is unpredictable. Simi­
larly, the ILC is unpredictable in the PSW stored during execution of the
store-status function and when the PSW is displayed.
For supervisor-call and program inter­
ruptions, a nonzero ILC identifies in halfwords the length of the instruction
that was last executed. Whenever an
instruction is executed by means of
EXECUTE, instruction-length code 2 is
set to indicate the length of EXECUTE
and not that of the target instruction.
The value of a nonzero instruction­
length code is related to the leftmost
two bits of the instruction. The value
does not depend on whether the operation
code is assigned or on whether the
instruction is installed. The following
table summarizes the meaning of the
instruction-length code:
ILC Instr
Bits Instruction
Decimal Binary 0-1 Length 0 00 Not available 1 01 00 One halfword
2 10 01 Two halfwords
2 10 10 Two halfwords
3 11 11 Three halfwords
Instruction-length code 0, after a
program interruption, indicates that the
instruction address stored in the old PSW does not identify the instruction
causing the interruption.
An ILC of 0 occurs when a specification
exception due to a PSW-format error is recognized as part of early exception
recognition and the PSW has been intro­
duced by LOAD PSW or an interruption.
(See the section "Exceptions Associated
with the PSW" later in this chapter.)
In the case of LOAD PSW, the instruction
address of LOAD PSW or EXECUTE has been replaced by the instruction address of
the new PSW. When the invalid PSW is introduced by an interruption, the PSW­ format error cannot be attributed to an
instruction. On some models without the translation facility, an ILC of 0 occurs also when
an addressing exception or a protection
exception is recognized for a store-type
reference. In these cases, the inter­
ruption due to the exception is delayed,
the length of time or number of
instructions of the delay being unpre­
dictable. Neither the instruction
address of the instruction causing the
exception nor the length of the last­
executed instruction is made available
to the program. This type of inter­
ruption is sometimes referred to as an
imprecise program interruption.
In the case of LOAD PSW and the
supervisor-call interruption, a PER event may be indicated concurrently with
a specification exception having an ILC
of O. Chapter 6. Interruptions 6-7

IlC on Instruction-Fetching Exceptions
When a program interruption occurs
because of an exception that prohibits
access to the instruction, the
instruction-length code cannot be set on
the basis of the first two bits of the
instruction. As far as the significance
of the IlC for this case is concerned,
the following two situations are distin­
guished:
1. When an odd instruction address
causes a specification exception to
be recognized or when an
addressing, protection, or
translation-specification exception is encountered on fetching an instruction, the IlC is set to 1,
2, or 3, indicating the multiple of
2 by which the instruction address
has been incremented. It is unpre­
dictable whether the instruction
address is incremented by 2, 4, or
6. By reducing the instruction
address in the old PSW by the number of halfword locations indi­
cated in the ILC, the instruction
address originally appearing in the PSW may be obtained. 2. When a segment-translation or
page-translation exception is
recognized while fetching an
instruction, including the target
instruction of EXECUTE, the ILC is
arbitrarily set to 1, 2, or 3. In
this case, the operation is nulli­
fied, and the instruction address
is not incremented.
The ILC is not necessarily related to
the first two bits of the instruction
when the first halfword of an instruc­
tion can be fetched but an access excep­
tion is recognized on fetching the
second or third halfword. The IlC may
be arbitrarily set to 1, 2, or 31n
these cases. The instruction address is
or is not updated, as described in situ­ ations 1 and 2 above.
When any exceptions other than segment
translation or page translation are
encountered on fetching the target
instruction of EXECUTE, the IlC is 2. Programming Notes
1. A nonzero instruction-length code
for a program interruption indi­
cates the number of halfword
locations by which the instruction
address in the program old PSW must
be reduced to obtain the instruc­
tion address of the last
instruction executed, unless one of
the following situations exists:
6-8 System/370 Principles of Operation a. The interruption an exception nullification.
is caused
resulting
by
in
b. An interruption for a PER event occurs before the execution of
an interruptible instruction is
completed, and no other
program-interruption condition
is indicated concurrently.
c. The interruption is caused by a PER event due to LOAD PSW or a
branch or linkage instruction,
including SUPERVISOR CALL (but
not including MONITOR CALL). d. The interruption is caused by
an access exception encountered
in fetching an instruction, and
the instruction address has
been introduced into the PSW by
a means other than sequential
operation (by a branch instruc­
tion, LOAD PSW, an
interruption, or conclusion of
an IPL sequence). e. The interruption is caused by a
specification exception because
of an odd instruction address.
f. The interruption is caused by
an early specification excep­
tion or by an access exception
encountered in fetching an
instruction, and changes have
been made to a parameter that
controls the relation between
instruction addresses and real
addresses. The relation between instruction addresses
and real addresses can be
changed without introducing an
entire new PSW by switching
from the real mode, primary­
space mode, or secondary-space
mode to a different mode, or by
changing one or more of the
translation parameters in
control registers 0, 1, and 7.
The early specification excep­
tion can be caused by executing
STORE THEN OR SYSTEM MASK or
SET SYSTEM MASK, which switches
to or from the real mode while
introducing invalid values in bit positions 0-7 of an EC-mode PSW. For situations a and b above, the
instruction address in the PSW is
not incremented, and the instruc­
tion designated by the instruction
address is the same as the last one
executed. These situations are the
only ones in which the instruction
address in the old PSW identifies
the instruction causing the excep­
tion.
For situations c, d, and e, the
instruction address has been
replaced as part of the operation,