Compa t
Compatibility among System/370 Models
Compatibility between System/360 and System/370
System
Availability
This publication describes the IBM
System/370 architecture.
attributes as
that is, the conceptual structure and
functional behavior of
distinct from the organization of the
data flow, the logical design, the phys
ical design, and
dissimilar machine implementations may
conform to a single architecture. When
the execution of programs on different
machine implementations produces the
results that
architecture, the implementations
System/370 is
several generations of compatible
general-purpose systems, starting with
System/360 as
porates
facilities, which are
is a facility that
locations in
reduces the addressing constraints
on both control programs and prob
lem programs,
freedom in program design.
efficient and effective utilization
of main storage. When one of the
operating systems for virtual stor
age is used, dynamic address
translation allows the use of up to
16,777,216 bytes of virtual
storage. Two page sizes (2K and 4K
bytes) and two
and 1M bytes) are provided,
although some models offer only the
64K-byte-segment size
models offer only the 4K-byte-page
size. Extensions to this facility
use of which increases the effec
tive size of the translation
lookaside buffer and thus improves
tion INVALIDATE
all models.
extended by low-address protection,
protection of storage locations at
effective addresses
which are vital to the control
program. Segment protection, which
is available on some models,
provides
in the segment-table entry. When
the bit is one, an attempt to store
in the segment causes a protection
exception to be recognized.
Extended real addressing, which is
an extension to dynamic address
translation, provides the
the capability of addressing up to
64M bytes of real storage. This is
accomplished by the use of bits 13
and 14 of the page-table entry,
which serve as the high-order bits
of the page-frame real address when
4K-byte pages
larger address
real address provided by dynamic
address translation and to the
address provided by the
ADDRESS instruction.
Channel indirect data addressing, a
companion facility to dynamic
address translation, provides
assistance in translating data
addresses for
permits a single channel-command
word to control
data that spans noncontiguous areas
of main storage. In the basic form
the indirect-data-address word
contains a 24-bit address. This
becomes a 31-bit address when the
31-bit-IDAW facility is installed.
Multiprocessing provides for the
interconnection of
system availability and share data
and resources. It includes facili
programmed and special machine
signaling between
programmed reassignment of the
first 4K bytes of real storage for
each