Emergency signal
External call
TOO-clock sync checkClock comparator CPU timer Service signal
Theinterval timer, interrupt key, and
the external signals 2-7 are of equal
priority;if more than one of these
conditions is pending and allowed, the
conditions are indicated concurrently.
All other requests are honored oneat a
time. When more than one emergencysignal request exists at a time or when
more than one malfunction-alert request
exists ata time, the request associated
with the smallestCPU address is honored
first.CLOCK COMPARATOR An interruption request for the clock
comparator exists whenever either of the
following conditions is met:
1. TheTOO clock is in the set or
not-set state, and the value of the
clock comparatoris less than the
value in the compared portion of
theTOO clock, both compare values
being considered unsigned binary
integers.
2. The clock comparator is installed,
and theTOO clock is in the error
or not-operational state.
If the condition responsible for the
request is removed before the request is
honored, the request does not remain
pending, and no interruption occurs.
Conversely, the request is not cleared
by the interruption, and, if the condi
tion persists, more than one
interruption may result froma single
occurrence of the condition.
When theTOO clock accessed by a CPU is
set or changes state, interruption
conditions, if any, that are due to the
clock comparator mayor may not be
recognized for up to1.048576 seconds
after the change.
The subclass-mask bit is in bit position20 of control register O. This bit is initialized to zero.
The clock-comparator condition is indi
cated by an external-interruption code
of1004 hex. CPU TIMER
An interruption request
timer exists whenever
for theCPU the CPU-timer value is negative (bit 0 of the CPU timer is one). If the value is made
positive before the request is honored,
the request does not remain pending, and
no interruption occurs.Conversely, the request is not cleared by the inter
ruption, and, if the condition persists,
more than one interruption may occur
from a single occurrence of the condi
tion.
When theTOO clock accessed by a CPU is set or changes state, interruption
conditions, if any, that are due to theCPU timer mayor may not be recognized
for up to1.048576 seconds after the
change.
The subclass-mask bit isin bit position
21 of control registerO. This bit is
initialized to zero.
TheCPU-timer condition is indicated by an external-interruption code of 1005 hex. EMERGENCY SIGNAL An interruption request for an emergency
signal is generated when theCPU accepts
the emergency-signal order specified bya SIGNAL PROCESSOR instruction address
ing thisCPU. The instruction may have
been executed by thisCPU or by another CPU in the configuration. The request
is preserved andremains pending in the
receivingCPU until it is cleared. The
pending requestis cleared when it caus
es an interruption and byCPU reset.
Facilities are provided for holding a
separate emergency-signal request pend
ing in the receivingCPU for each CPU in
the configuration, including the receiv
ingCPU itself.
The subclass-mask bit is in bit position
17 of control register o. This bit is
initialized to zero.
The emergency-signal condition is indi
cated by an external-interruption code
of1201 hex. The address of the CPU that executed the SIGNAL PROCESSOR instruction is stored at real locations
132-133.
EXTERNALCALL An interruption request for an external
call is generated when theCPU accepts
the external-call order specified by aSIGNAL PROCESSOR instruction addressing
thisCPU. The instruction may have been
executed by thisCPU or by another CPU in the configuration. The request is
preserved and remains pending in the
receivingCPU until it is cleared. The Chapter 6. Interruptions 6-11
External call
TOO-clock sync check
The
the external signals 2-7 are of equal
priority;
conditions is pending and allowed, the
conditions are indicated concurrently.
All other requests are honored one
time. When more than one emergency
more than one malfunction-alert request
exists at
with the smallest
first.
comparator exists whenever either of the
following conditions is met:
1. The
not-set state, and the value of the
clock comparator
value in the compared portion of
the
being considered unsigned binary
integers.
2. The clock comparator is installed,
and the
or not-operational state.
If the condition responsible for the
request is removed before the request is
honored, the request does not remain
pending, and no interruption occurs.
Conversely, the request is not cleared
by the interruption, and, if the condi
tion persists, more than one
interruption may result from
occurrence of the condition.
When the
set or changes state, interruption
conditions, if any, that are due to the
clock comparator mayor may not be
recognized for up to
after the change.
The subclass-mask bit is in bit position
The clock-comparator condition is indi
cated by an external-interruption code
of
An interruption request
timer exists whenever
for the
positive before the request is honored,
the request does not remain pending, and
no interruption occurs.
ruption, and, if the condition persists,
more than one interruption may occur
from a single occurrence of the condi
tion.
When the
conditions, if any, that are due to the
for up to
change.
The subclass-mask bit is
21 of control register
initialized to zero.
The
signal is generated when the
the emergency-signal order specified by
ing this
been executed by this
is preserved and
receiving
pending request
es an interruption and by
Facilities are provided for holding a
separate emergency-signal request pend
ing in the receiving
the configuration, including the receiv
ing
The subclass-mask bit is in bit position
17 of control register o. This bit is
initialized to zero.
The emergency-signal condition is indi
cated by an external-interruption code
of
132-133.
EXTERNAL
call is generated when the
the external-call order specified by a
this
executed by this
preserved and remains pending in the
receiving