is preserved and remains pending in the
receiving CPU until it is cleared. The
pending request is cleared when it caus­
es an interruption and by CPU reset.
Facilities are provided for holding a
separate malfunction-alert request pend­
ing in the receiving CPU for each of the
other CPUs in the configuration.
Removal of a CPU from the configuration
does not generate a malfunction-alert
condition.
The subclass-mask bit is in bit position
16 of control register O. This bit is initialized to zero.
The malfunction-alert condition is indi­
cated by an external-interruption code
of 1200 hex. The address of the CPU
that generated the condition is stored
at real locations 132-133.
SERVICE SIGNAL
An interruption request for a service
signal is generated upon the completion
of certain configuration-control and
maintenance functions, such as those initiated by means of the model­
dependent DIAGNOSE instruction. A
32-bit parameter is provided with the
interruption to assist the program in
determining the operation for which the
interruption is reported.
Service signal is a floating inter­
ruption condition and is presented to
the first CPU in the configuration which
can accept the interruption. The pend­
ing request is cleared when it causes an
interruption in anyone of the CPUs and
also by subsystem reset.
The subclass-mask bit is in bit position
22 of control register O. This bit is
initialized to zero.
The service-signal condition is indi­
cated by an external-interruption code
of 2401 hex. A 32-bit parameter is
stored at real locations 128-131. TOO-CLOCK SYNC CHECK
The TOD-clock-sync-check condition indi­
cates that more than one TOO clock
exists in the configuration, and that
the rightmost 32 bits of the clocks are
not running in synchronism.
An interruption request for a TOO-clock sync check exists when the TOO clock
accessed by this CPU is running (that is, the clock is in the set or not-set
state), the clock accessed by any other
CPU in the configuration is running, and
bits 32-63 of the two clocks do not
match. When a clock is set or changes
state, or when a running clock is added
to the configuration, a delay of up to 1.048576 seconds (2
20
microseconds) may
occur before the mismatch condition is recognized.
When only two TOO clocks are in the
configuration and either or both of the
clocks are in the error, stopped, or
not-operational state, it is unpredict­
able whether a TOD-clock-sync-check
condition is recognized; if the condi­
tion is recognized, it may continue to
persist up to 1.048576 seconds after
both clocks have been running with the
rightmost 32 bits matching. However, in
this case, the condition does not
persist if one of the TOO clocks is
removed from the configuration.
When more than one CPU shares a TOO clock, only the CPU with the smallest
CPU address among those sharing the
clock indicates a TOD-clock-sync-check
condition associated with that clock.
If the condition responsible for the
request is removed before the request is
honored, the request does not remain
pending, and no interruption occurs.
Conversely, the request is not cleared
by the interruption, and, if the condi­
tion persists, more than one
interruption may result from a single
occurrence of the condition.
The subclass-mask bit is in bit position
19 of control register O. This bit is initialized to zero.
The TOD-clock-sync-check condition is
indicated by an external-interruption
code of 1003 hex. I/O INTERRUPTION The input/output (I/O) interruption
provides a means by which the CPU
responds to conditions originating in I/O devices and channels.
A request for an I/O interruption may
occur at any time, and more than one
request may occur at the same time. The
requests are preserved and remain pend­
ing in channels or devices until
accepted by the CPU, or until cleared by
some other means, such as subsystem
reset.
The I/O interruption occurs at the
completion of a unit of operation.
Priority is established among requests
so that only one interruption request is
processed at a time. For more details,
see the section "Input/Output Inter­
ruptions" in Chapter 13, "Input/Output
Operations."
Chapter 6. Interruptions 6-13
When the CPU becomes enabled for I/O interruptions and a channel has estab­
lished priority for a pending 1/0- interruption condition, the interruption
occurs at the completion of the instruc­
tion execution or interruption that
causes the enabling.
An I/O interruption causes the old PSW to be stored at real location 56, a
channel-status word to be stored at real
location 64, and a new PSW to be fetched
from real location 120. Upon detection
of equipment errors, additional informa­
tion may be stored in the form of a
limited channel logout at real locations
176-179, and in the form of a full chan­
nel logout at real locations 256-351 or
in the I/O-extended-Iogout area starting
at the absolute location designated by
the contents of real locations 173-175.
When the old PSW specifies the EC mode,
the I/O address identifying the channel
and device causing the interruption is
stored at real locations 186-187, and
the measurement byte is stored at real
location 185. When the old PSW speci­
fies the BC mode, the interruption code
in PSW bit positions 16-31 contains the I/O address, and the instruction-length
code in the PSW is unpredictable.
A nonzero value for the measurement byte
is part of the
facility. When
installed, zeros
location.
start-I/O-fast-queuing
this facility is not are stored at this
An I/O interruption can occur only while
the CPU is enabled for interruption by
the channel presenting the request.
Mask bits in the PSW and channel masks
in control register 2 determine whether
the CPU is enabled for interruption by a
channel; the method of control depends
on whether the current PSW specifies the EC or BC mode.
The channel-mask bits in control regis­
ter 2 start at bit position 0 and extend
for at least as many contiguous bit
positions as required to control inter­
ruptions from the channel with the
greatest installed channel address which
may be connected to this CPU. The
assignment is such that a bit is
assigned to the channel whose address is
equal to the position of the bit in
control register 2. Installed channel­
mask bits are initialized to onei the
state of the remaining bits in control
register 2 is unpredictable.
When the current PSW specifies the EC mode, each channel is controlled by the I/O-mask bit, PSW bit 6, and by the
corresponding channel-mask bit in
control register 2; the channel can
cause an interruption only when the I/O-mask bit is one and the correspond­
ing channel-mask bit is one. The
channel causing the interruption must be
6-14 System/370 Principles of Operation a member of a channel set which is
connected to this CPU. When the current PSW specifies the BC mode, interruptions from channels 6 and
up are controlled by the I/O-mask bit, PSW bit 6, in conjunction with the
corresponding channel-mask bit: the
channel can cause an interruption only when the I/O-mask bit is one and the
corresponding channel-mask bit is one.
Interruptions from channels 0-5 are
controlled by channel-mask bits 0-5 in
the PSW: an interruption can occur only
when the mask bit corresponding to the
channel is one. In the BC mode, bits 0-5 in control register 2 do not partic­
ipate in controlling I/O interruptions;
they are, however, preserved in the
control register if the corresponding
channels are installed. MACHINE-CHECK INTERRUPTION The machine-check interruption is a means for reporting to the program the
occurrence of equipment malfunctions.
Information is provided to assist the
program in determining the source of the
fault and extent of the damage.
A machine-check interruption causes the
old PSW to be stored at real location 48
and a new PSW to be fetched from real
location 112. When the old PSW speci­
fies the BC mode, the contents of the
interruption-code and ILC fields in the
old PSW are unpredictable.
The cause and severity of the malfunc­
tion are identified by a 64-bit
machine-cheek-interruption code stored
at real locations 232-239. Further
information identifying the cause of the
interruption and the location of the
fault may be stored at real locations
216-511 and in the area starting with
the real location designated by the
contents of control register 15.
The interruption action and the storing
of the associated information are under
the control of PSW bit 13 and bits in
control register 14. See Chapter 11, "Machine-Check Handling," for more
detailed information. PROGRAM INTERRUPTION Program interruptions are used to report
exceptions and events which occur during
execution of the program.
A program interruption causes the old PSW to be stored at real location 40 and
a new PSW to be fetched from real
location 104.
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