receiving CPU until it is cleared. The
pending request is cleared when
es an interruption and by CPU reset.
Facilities are provided for holding a
separate malfunction-alert request pend
ing
other CPUs in the configuration.
Removal of a CPU from the configuration
does not generate a malfunction-alert
condition.
The subclass-mask bit is in bit position
16 of control register
The malfunction-alert condition is indi
cated by an external-interruption code
of
that generated the condition is stored
at real locations 132-133.
SERVICE SIGNAL
An interruption request for a service
signal
of certain configuration-control and
maintenance functions, such
dependent
32-bit parameter is provided with the
interruption to assist the program in
determining the operation for which the
interruption is reported.
Service signal
ruption condition and
the first CPU
can accept the interruption. The pend
ing request is cleared when it causes an
interruption in anyone of the CPUs and
also by subsystem reset.
The subclass-mask bit is in bit position
22 of control register
initialized to zero.
The service-signal condition is indi
cated by an external-interruption code
of
stored at real locations 128-131.
The TOD-clock-sync-check condition indi
cates that more than one
exists in the configuration, and that
the rightmost 32 bits of the clocks are
not running in synchronism.
An interruption request for a
accessed by this CPU is running (that
state), the clock accessed by any other
CPU in the configuration is running, and
bits 32-63 of the two clocks do not
match. When a clock is set or changes
state, or when a running clock is added
to the configuration, a delay of up to
20
occur before the mismatch condition
When only two
configuration and either or both of the
clocks are in the error, stopped, or
not-operational state, it is unpredict
able whether a TOD-clock-sync-check
condition is recognized; if the condi
tion is recognized, it may continue to
persist up to
both clocks have been running with the
rightmost 32 bits matching. However, in
this case, the condition does not
persist if one of the
removed from the configuration.
When more than one CPU shares a
CPU address among those sharing the
clock indicates a TOD-clock-sync-check
condition associated with that clock.
If the condition responsible for the
request is removed before the request is
honored, the request does not remain
pending, and no interruption occurs.
Conversely, the request is not cleared
by the interruption, and, if the condi
tion persists, more than one
interruption may result from
occurrence of the condition.
The subclass-mask bit is in bit position
19 of control register
The TOD-clock-sync-check condition is
indicated by an external-interruption
code of
provides a means by which the CPU
responds to conditions originating in
A request for an
occur at any time, and more than one
request may occur at the same time. The
requests are preserved and remain pend
ing in channels or devices until
accepted by the CPU, or until cleared by
some other means, such as subsystem
reset.
The
completion of a unit of operation.
Priority is established among requests
so that only one interruption request is
processed at a time. For more details,
see the section "Input/Output Inter
ruptions" in Chapter 13, "Input/Output
Operations."
Chapter 6. Interruptions 6-13