The segment-translation exception is
indicated by a program-interruption code
of 0010 hex (or 0090 hex if a concurrent PER event is indicated).
Significance Exception
A significance exception is
when the result fraction in
point addition or subtraction
recognized
floating­ is zero. The interruption may be disallowed by
the significance mask (PSW bit 23 in the EC mode and PSW bit 39 in the BC mode).
The operation is completed. The signif­
icance mask also affects the result of the operation. When the mask bit is
zero, the operation is completed by
replacing the result with a true zero. When the mask bit is one, the operation
is completed without further change to the characteristic of the result.
The instruction-length code is 1 or 2. The significance exception is indicated
by a program-interruption code of XXOE hex (or XX8E hex if a concurrent PER event is indicated), where XX is the
exception-extension code.
Space-Switch Event A space-switch event is recognized at
the completion of a PROGRAM CALL with
space switching (PC-ss) or a PROGRAM TRANSFER with space switching (PT-ss) when any of the following is true:
1. The space-switch-event-control bit,
bit 31 of control register 1, is one before the operation.
2. The space-switch-event-control bit
is one after the operation.
3. A PER event is reported.
The old PASN, which is in the right half of control register 4 before the
execution of the instruction PC-ss or PT-ss, is stored at real locations
146-147. The old space-switch-event­
control bit is placed in bit position 0 and zeros are placed in bit positions
1-15 at real locations 144-145.
The operation is completed. The instruction-length code is 2. I The space-switch event is indicated by a I program-interruption code of OOIC hex I (or 009C hex if a concurrent PER event is indicated). Programming Notes
1. The space-switch event permits the
control program to galn control
whenever a program enters or leaves
a particular address space. The
space-switch-event-control bit is loaded into control register 1,
along with the remaining bits of
the primary segment-table desig­
nation, whenever control register 1
is loaded.
2. The space-switch event may be useful in obtaining programmed
author;zat;on checking, in caus;ng
additional trace information to be
recorded, or in enabling or disabl­
ing the CPU for PER or tracing.
3. Bit 95 of the ASN-second-table
entry (ASTE) is loaded into bit
position 31 of control register 1 as part of the PC-ss and PT-ss operations. If bit 95 of the ASTE
for a particular address space is
set to one, then a space-switch
event is recognized when a program
enters or leaves the address space
by means of either a PC-ss or a PT-ss. 4. The occurrence of a space-switch
event at the completion of a PC-ss or PT-ss when any PER event is
indicated permits the control
program to determine the address
space from which the instruction
causing the PER event was fetched. Special-Operation Exception
A special-operation exception is recog­ nized when any of the following is true:
1. Execution of SET SYSTEM MASK is attempted in the supervisor state
and the SSM-suppression control,
bit 1 of control register 0, is
one.
2. Execution of any of the following
instructions is attempted with OAT off: EXTRACT PRIMARY ASN EXTRACT SECONDARY ASN INSERT ADDRESS SPACE CONTROL INSERT VIRTUAL STORAGE KEY MOVE TO PRIMARY MOVE TO SECONDARY SET ADDRESS SPACE CONTROL SET SECONDARY ASH 3. Execution of PROGRAM CALL or PROGRAM TRANSFER is attempted, and Chapter 6. Interruptions 6-25

the CPU is not in the primary-space
mode.
4. Execution of LOAD ADDRESS SPACE PARAMETERS, PROGRAM CALL with space
switching (PC-ss), PROGRAM TRANSFER
with space switching (PT-ss), or
SET SECONDARY ASN (SSAR-cp or
SSAR-ss) is attempted, and the
ASN-translation control, bit 12 of
control register 14, is zero.
5. Execution of PROGRAM CALL or PROGRAM TRANSFER is attempted and,
the subsystem-linkage control, bit
o of control register 5, is zero.
6. Execution of SET ADDRESS SPACE CONTROL, MOVE TO PRIMARY, or MOVE TO SECONDARY is attempted, and the
secondary-space control, bit 5 of
control register 0, is zero.
7. The storage-key 4K-byte-block
facility is installed; execution of
the instruction INSERT STORAGE KEY, RESET REFERENCE BIT, or SET STORAGE KEY is attempted; and the storage­
key-exception control, bit 7 of
control register 0, is zero.
The operation is suppressed.
The instruction-length code is 1, 2, or
3, and indicates the length of the
instruction causing the exception.
The special-operation exception is indi­
cated by a program-interruption code of 0013 hex (or 0093 hex if a concurrent PER event is indicated). Specification Exception
A specification exception is recognized
when any of the following is true:
1. A one is introduced into an unas­
signed bit position of an EC-mode PSW (that is, any of bit positions 0, 2-4, 17, or 24-39). This is
handled as an early PSW specifica­ tion exception.
2. A PSW is introduced in which the EC mode is specified (PSW bit 12 is
one) in a CPU that does not have the translation facility installed.
This is handled as an early PSW specification exception.
3. A one is introduced into an EC-mode PSW bit position, other than in the I/O-mask or program-mask field,
specifying a mode or facility that
is not installed in the CPU. For
example, bit 16 is one, and DAS is
not installed. This is handled as
an early PSW specification excep­
tion.
6-26 System/370 Principles of Operation 4. The PSW contains an odd instruction
address.
5. An operand address does not desig­
nate an integral boundary in an
instruction requiring such
integral-boundary designation.
6. An odd-numbered general register is
designated by an R field of an
instruction that requires an even­ numbered register designation.
7. A floating-point register other
than 0, 2, 4, or 6 is designated
for a short or long operand, or a
floating-point register other than
o or 4 is designated for an
extended operand.
8. The multiplier or divisor in deci­
mal arithmetic exceeds 15 digits
and sign.
9. The length of the first-operand
field is less than or equal to the
length of the second-operand field
in decimal multiplication or divi­
sion. 10. Bit positions 8-11 of MONITOR CALL do not contain zeros.
11. Bits 20-22 of the second-operand
address of SET ADDRESS SPACE CONTROL are not all zeros.
12. The leftmost eight bits of the
general register designated by the R2 field of PROGRAM TRANSFER are
not zeros.
13. Execution of PROGRAM CALL, PROGRAM TRANSFER, or SET SECONDARY ASN is attempted with DAS tracing enabled,
and (1) bits 29-31 of the trace­
table designation contained in the
word at logical location 84 are not
all zeros, or (2) the new value of
bits 27-31 of the trace-table-entry header would not be zero.
14. The storage address in INSERT STORAGE KEY or SET STORAGE KEY does
not have zeros in the four right­
most bit positions.
The execution of the instruction identi­
fied by the old PSW is suppressed.
However, for early PSW specification
exceptions (causes 1-3), the operation
that introduces the new PSW is
completed, but an interruption occurs immediately thereafter.
Except as noted below, the instruction­
length code (ILC) is 1, 2, or 3, indi­ cating the length of the instruction causing the exception. When the instruction address is odd
(cause 4), it is unpredictable whether
the ILC is 1, 2, or 3.