When the exception is recognized because
of an early PSW specification exception,
(causes 1-3), and the exception has been introduced by LOAD PSW or an inter­ ruption, the ILC is o. When the excep­
tion is introduced by SET SYSTEM MASK or
by STORE THEN OR SYSTEM MASK, the ILC is 2.
The specification exception is indicated
by a program-interruption code of 0006 hex (or 0086 hex if a concurrent PER event is indicated).
Programming Note See the section "Exceptions Associated
with the PSW" in this chapter for a
definition of when the exceptions asso­
ciated with the PSW are recognized.
Translation-Specification Exception
A translation-specification exception is recognized when translation of a virtual
address is attempted and any of the
following is true:
1. Bit positions 8-12 of control
register 0 do not contain one of
the codes 01000, 01010, 10000, or 10010. When the translation facil­
ity is installed but the 1M-byte
segment size is not provided, the exception is recognized when bit
positions 8-12 do not contain one of the codes 01000 or 10000. On models offering only the 4K-byte
page size, the exception is recog­ nized when bit positions 8-12 do
not contain the code 10000. 2. The segment-table entry used for the translation is valid and bit
positions 4-7 and 29-30 in the
ent ry do not conta in zero s. (On some models, these bit positions
are ignored and not checked for
zeros.) When the segment­ protection facility is installed,
bit 29 of the segment-table entry
is used to indicate segment
protection and need not be zero.
When the common-segment facility is
installed, bit 30 is interpreted as
the common-segment bit and need not
be zero.
3. The page-table entry used for the
translation is valid and bit posi­
tion 14, when 2K-byte pages are
used, or bit posltions 13-14, when 4K-byte pages are used, in the
entry do not contain zeros. When the extended-real-addressing facil­
ity is installed, and when 4K-byte
pages are used, bit positions 13 and 14 of the page-table entry are the extended-storage-address bits
and need not be zeros.
The exception is recognized only as part
of the execution of an instruction using
address translation, that is, when DAT
is on and a logical address, instruction
address, or virtual address must be
translated, or when LOAD REAL ADDRESS or
INVALIDATE PAGE TABLE ENTRY is executed.
Cause 1 is recognized on any translation
attempt; causes 2 and 3 are recognized
only for table entries that are actually
used.
The unit of operation is suppressed.
When the exception occurs during fetch­
ing of an instruction, it is unpredict­
able whether the ILC is 1, 2, or 3.
When the exception occurs during the
fetching of the target of EXECUTE, the
ILC is 2.
When the exception occurs during a reference to an operand location, the
instruction-length code (ILC) is 1, 2,
or 3 and indicates the length of the
instruction causing the exception.
The translation-specification exception
is indicated by a program-interruption
code of 0012 hex (or 0092 hex if a
concurrent PER event 1S indicated). Programming Note When a translation-specification excep­
tion is recognized in the process of
translating an instruction address, the operation is suppressed. In this case, the instruction-length code (ILC) is needed to derive the address of the
instruction, as the instruction address
in the old PSW has been incremented by
the amount indicated by the ILC. In the
case of segment-translation and page­
translation exceptions, the operation is nullified, the instruction address in
the old PSW identifies the instruction, and the ILC may be arbitrarily set to 1, 2, or 3. Unnormalized-Operond Exception An unnormalized-operand exception is recognized when, in a vector floating­ point divide or multiply operation, a
source-operand element has a nonzero fraction with a leftmost hexadecimal
digit of zero. For more details, see the pub lie uti 0 n I B i1 S y c; t em / 3 7 0 Vee tor Ooerations, SA22-7125.
The unit of operation is inhibited. The instruction-length code is 2.
Chapter 6. Interruptions 6-27

The unnormalized-operand exception is
indicated by a program-interruption code
of XX1E hex (or XX9E hex if a concurrent PER event is indicated), where XX is the
exception-extension code.
Vector-Operation Exception
A vector-operation exception is recog­ nized when a vector-facility instruction
is executed while bit 14 of control
register 0 is zero on a CPU which has
the vector facility installed and avail­
able. The vector-operation exception is
also recognized when a vector-facility
instruction is executed and the vector
facility is not installed or available on this CPU, but the facility can be
made available to the program either on
this CPU or another CPU in the config­
uration. When a vector-facility instruction is executed, and the vector facility is not
installed on any CPU which is or can be
placed in the configuration, it depends on the model whether a vector-operation exception or an operation exception is
recognized. The operation is
vector-operation
recognized.
nullified when exception the i s The instruction-length code is 2 or 3.
6-28 System/370 Principles of Operation The vector-operation exception is indi­
cated by a program-interruption code of 0019 hex (or 0099 hex if a concurrent PER event is indicated).
COLLECTIVE PROGRAM-INTERRUPTION NAMES
For the sake of convenience, certain
program exceptions are grouped together
under a single collective name. These
collective names are used when it is necessary to refer to the complete set of exceptions, such as in instruction
definitions. Three collective names are
used:
Access exceptions
ASN-translation exceptions Trace exceptions
The individual exceptions and their
priorities are listed in the section "Multiple-Program-Interruption Condi­ tions" in this chapter. RECOGNITION OF ACCESS EXCEPTIONS The figure "Handling of Access Exceptions" summarlzes the conditions
that can cause access exceptions and the action taken when they are encountered.