therefrre, the reverse of the order in which the PSWs are fetched.
If the new PSW for a program inter­ ruption does not specify the wait state
and has an odd instruction address, or
causes an access exception to be recog­
nized, another program interruption
occurs. Since this second interruption
introduces the same unacceptable PSW, a string of interruptions is established.
These program exceptions are recognized as part of the execution of the follow­
ing instruction, and the string may be
broken by an external, I/O, machine­ check, or restart interruption or by the
stop function.
If the new PSW for a program inter­ ruption contains a one in an unassigned
bit position of an EC-mode PSW, or if it specifies the EC mode in a CPU that does
not have the EC mode, or if it specifies any other facility that is not installed
on the CPU, another program interruption
occurs. This condition is of higher
priority than restart, I/O, external, or
repressible machine-check conditions, or
the stop function, and CPU reset has to be used to break the string of inter­
ruptions.
A string of interruptions for other
interruption classes can also exist if
the new PSW allows the interruption
which has just occurred. These include
machine-check interruptions, external
interruptions, and I/O interruptions due
to PCI conditions generated because of
CCWs which form a loop. Furthermore, a string of interruptions involving more
than one interruption class can exist.
For example, assume that the CPU timer is negative and the CPU-timer subclass
mask is one. If the external new PSW has a one in an unassigned bit position
in the EC mode, and the program new PSW is enabled for external interruptions,
then a string of interruptions occurs, alternating between external and
program. Even more complex strings of
interruptions are possible. As long as
more interruptions must be serviced, the string of interruptions cannot be broken
by employing the stop function; CPU reset is required. Similarly, CPU reset has to be invoked
to terminate the condition that exists
when an interruption is attempted with a
prefix value designating a storage
location that is not available to the CPU. On some models, when an excessive string
of consecutive interruptions is detected
which cannot be broken by means of the stop function, the CPU enters a special state that can be exited only by use of CPU reset.
Interruptions for all requests for which
the CPU is enabled occur before the CPU is placed in the stopped state. When the CPU is in the stopped state, restart
has the highest priority. Programming Note The order in which concurrent inter­
ruption requests are honored can be
changed to some extent by masking.
Chapter 6. Interruptions 6-37