ASH-Translation Exceptions The ASH-translation exceptions are those exceptions which are common to the proc- ess of translating an ASH in the
instructions PROGRAM CAll, PROGRAM TRAHSFER, and SET SECOHDARY ASH. The exceptions and the priority in which
they are detected are shown in the figure "Priority of ASH-Translation Exceptions." 1. Addressing exception for access
to ASH-first-table entry.
2.
3.
4.
5.
AFX-translation exception due to I bit (bit 0) in ASH-first­ table entry being one. ASH-translation-specification
exception due to invalid ones
(bits 1-7, 28-31) in ASH-first­ table entry.
Addressing exception for access
to ASH-second-table entry.
ASX-translation exception due to I bit (bit 0) in ASH-second­ table entry being one.
6. ASH-translation-specification
exception due to invalid ones
(bits 1-7, 30, 31, 60-63, 97- 103) in ASH-second-table entry.
Priority of ASH-Translation Exceptions
Trace Exceptions
The trace exceptions are those exceptions which can be encountered while performing the implicit tracing
function. The exceptions, except for PER storage alteration, and their prior­
ity are shown in the figure "Priority of
Trace Exceptions." PER storage alter­ ation is recognized only if the
instruction is completed.
1 .
2.
3.A
3.B
4.
5.
Access exceptions (except for
protection) for the trace-table
designation at logical location
84. Specification exception due to
bits 29-31 of the word at
trace-header address in logical
location 84 not being zeros.
Access exceptions (including
low-address protection and seg­
ment protection) for first
doubleword of trace-table-entry header. Access exceptions (except for
protection) for third word of
trace-table-entry header. Specification exception if new
value of trace-entry address in trace header would not desig­
nate a 32-byte boundary.
Access exceptions (including
low-address protection and seg­ ment protection) for the trace
entry.
Priority of Trace Exceptions RESTART IHTERRUPTIOH The restart interruption provides a means for the operator or another CPU to
invoke the execution of a specified
program. The CPU cannot be disabled for
this interruption.
A restart interruption causes the old PSW to be stored at real location 8 and a new PSW, designating the start of the
program to be executed, to be fetched
from real location o. The instruction­
length code and interruption code are
not stored in the EC mode. In the BC mode, the instruction-length code in the PSW is unpredictable, and zeros are stored in the interruption-code field.
If the CPU is in the operating state,
the exchange of the PSWs occurs at the
completion of the current unit of opera­
tion and after all other pending inter­
ruption conditions for which the CPU is
enabled have been honored. In this
case, it depends on the model if the CPU temporarily enters the stopped state as
part of the execution of the restart
operation. If the CPU is in the stopped
state, the CPU enters the operating
state and exchanges the PSWs without
first honoring any other pending inter­
ruptions. Chapter 6. Interruptions 6-35

The restart interruption is initiated by
activating the restart key. When the
multiprocessing facility;s installed,
the operation can also be initiated at
the addressed CPU by executing a SIGNAL PROCESSOR instruction which specifies
the restart order.
When the rate control is set to the
instruction-step position, it is dictable whether restart causes a unit
of operation or additional interruptions
to be performed after the PSWs have been
exchanged. Programming Note
To perform a restart when the CPU is in
the check-stop state, the CPU has to be
reset. If the translation facility is
installed, resetting with loss of the least amount of information can be
accomplished by means of the system­
reset-normal key, which does not clear the contents of program-addressable
registers, including the control regis­
ters, but causes the channels to be
reset. The program-reset SIGNAL PROCES­ SOR order can be used to perform a
similar function. SUPERVISOR-CALL INTERRUPTION The supervisor-call interruption occurs
when the instruction SUPERVISOR CAll is
executed. The CPU cannot be disabled
for the interruption, and the inter­
ruption occurs immediately upon the
execution of the instruction.
The supervisor-call interruption causes
the old PSW to be stored at real
location 32 and a new PSW to be fetched
from real location 96.
The contents of bit positions 8-15 of
the SUPERVISOR CALL instruction are placed in the rightmost byte of the
interruption code. The leftmost byte of
the interruption code is set to zero.
The instruction-length code is 1, unless
the instruction was executed by means of EXECUTE, in which case the code is 2.
When the old PSW specifies the EC mode,
the interruption code is placed in real
locations 138-139, the instruction­
length code is placed in bit positions 5
and 6 of the byte at real location 137, with the other bits set to zeros, and
zeros are stored at real location 136.
When the old PSW specifies the BC mode, the interruption code and instruction­
length code are placed in the old PSW. 6-36 System/370 Principles of Operation PRIORITY OF INTERRUPTIONS During the execution of an instruction,
several interruption-causing events may
occur simultaneously. The instruction
may give rise to a program interruption,
a request for an external interruption may be received, equipment malfunction­
ing may be detected, an I/O-interruption
request may be made, and the restart key
may be activated. Instead of the
program interruption, a supervisor-call
interruption might occur; or both can
occur if PER is active. Simultaneous
interruption requests are honored in a
predetermined order.
An exigent machine-check condition has
the highest priority. When it occurs,
the current operation is terminated or
nullified. Program and supervisor-call
interruptions that would have occurred
as a result of the current operation may be eliminated. Any pending repressible
machine-check conditions may be indi­
cated with the exigent machine-check
interruption. Every reasonable attempt
is made to limit the side effects of an
exigent machine-check condition, and
requests for external, I/O, and restart
interruptions normally remain unaf­
fected.
In the absence of an exigent machine­
check condition, interruption requests
existing concurrently at the end of a
unit of operation are honored, in
descending order of priority, as
follows:
Supervisor call Program Repressible machine check
External
Input/output
Restart
The processing of multiple simultaneous
interruption requests consists in stor­
ing the old PSW and fetching the new PSW belonging to the interruption first
honored. This new PSW is subsequently
stored without the execution of any
instructions, and the new PSW associated
with the next interruption is fetched.
Storing and fetching of PSWs continues
until no more interruptions are to be
serviced. The priority is reevaluated
after each new PSW is loaded. Each
evaluation takes into consideration any
additional interruptions which may have
become pending. Additionally, external
and I/O interruptions, as well as
machine-check interruptions due to
repressible conditions, occur only if
the current PSW at the instant of evalu­
ation indicates that the CPU is
interruptible for the cause.
Instruction execution is resumed using
the last-fetched PSW. The order of
executing interruption subroutines is,