Programming Notes
1. An example of the use of the AND
instruction is given in Appendix A.
2. The AND instruction may be used to
set a bit to zero.
3. Accesses to the first operand of
AND (NI) and AND (NC) consist in
fetching a first-operand byte from
storage and subsequently storing
the updated value. These fetch and
store accesses to a particular byte
do not necessarily occur one imme­
diately after the other. Thus, the
instruction AND cannot be safely
used to update a location in stor­
age if the possibility exists that
another CPU or a channel may also
be updating the location. An exam­
ple of this effect is shown for OR
(01) in the section "Multiprogram­
ming and Multiprocessing Examples"
in Appendix A. BRANCH AND LINK
BALR R, , R:z [RR] , 05' I R t I R:z I 0 8 12 15
BAL R"D:z(X:z,B:z) [RX]
'45' I R, I X:z I B:z D:z 0 8 12 16 20 31
Information from the current PSW,
including the updated instruction
address, is loaded as link information
at the first-operand location. Subse­
quently, the instruction address is
replaced by the branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register R:z are used as the branch
address; however, when the R:z field is
zero, the operation is performed without
branching. The branch address is
computed before general register Rt is
changed.
The link information consists of the
instruction-length code (ILC), the
condition code (CC), the program mask
bits, and the updated instruction
address, arranged in the following
format:
Instruction Address
o 2 4 8 31
The instruction-length code is 1 or 2. Condition Code: unchanged.
The code remains Program Exceptions: None.
Programming Notes
1. An example of the use of the BRANCH AND LINK instruction is given in
Appendix A.
2. When the R, field in the RR format
is zero, the link information is
loaded without branching.
3. When BRANCH AND LINK is the target
instruction of EXECUTE, the
instruction-length code is 2.
4. The format and the contents of the
link information do not depend on
whether the PSW specifies the EC or BC mode. In both modes, the link
information is in the format of the
rightmost 32 bit positions of the BC-mode PSW. BRANCH AND SAVE
BASR R t , R:z [RR] '00' I R t I R:z I 0 8 12 15
BAS Rt ,0,(X
2
,B
2
)
[RX]
'4D' Rt X2 B, D2 0 8 12 16 20 31
The updated instruction address, with
eight zeros appended on the left, is
saved as link information at the first­
operand location. Subsequently, the
instruction address is replaced by the
branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register R2 are used as the branch
address; however, when the R, field is
zero, the operation is performed without
branching. The branch address is
computed before general register Rt is
changed. Chapter 7. General Instructions 7-9
Condition Code: unchanged. The code remains
Program Exceptions: Operation (if the branch-and-save
facility is not installed)
Programming Notes
1. An example of the use of the BRANCH AND SAVE instruction is given in Appendix A.
2. The BRANCH AND SAVE instruction
(BAS and BASR) may be used in place
of the BRANCH AND LINK instruction
(BAL and BALR) when it is desired
to obtain the instruction address
without the instruction-length
code, program mask, and condition
code.
BRANCH ON CONDITION BCR Mil R2 [RR]
, 07' I M t I R2 I 0 8 12 15 BC M
t ,D2(X2,B2) [RX]
'47' I M t I X
2 I B2 D2 o 8 12 16 20 31
The instruction address in the current PSW is replaced by the branch address if
the condition code has one of the values
specified by M
t
; otherwise, normal
instruction sequencing proceeds with the
updated instruction address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register R2 are used as the branch
address; however, when the R2 field is zero, the operation is performed without
branching.
The Mt field is used as a four-bit mask.
The four condition codes (0, 1, 2, and
3) correspond, left to right, with the
four bits of the mask, as follows: 7-10 System/370 Principles of Operation Instruction Mask
Condition Bit No. of Position Code Mask Value 0 8 8
1 9 4
2 10 2
3 11 1
The current condition code is used to
select the corresponding mask bit. If
the mask bit selected by the condition
code is one, the branch is successful.
If the mask bit selected is zero, normal
instruction sequencing proceeds with the
next sequential instruction.
When the Mt and R2 fields of BRANCH ON CONDITION (BCR) are all ones and all
zeros, respectively, a serialization and
checkpoint-synchronization function is
performed. Condition Code: unchanged.
The Program Exceptions: None.
Programming Notes
code remains
1. An example of the use of the BRANCH ON CONDITION instruction is given
in Appendix A.
2. When a branch is to depend on more
than one condition, the pertinent
condition codes are specified in
the mask as the sum of their mask
position values. A mask of 12, for
example, specifies that a branch is
to be made when the condition code
is 0 or 1.
3. When all four mask bits are zeros
or when the R2 field in the RR
format contains zero, the branch
instruction is equivalent to a
no-operation. When all four mask
bits are ones, that is, the mask
value is 15, the branch is uncondi­
tional unless the R2 field in the
RR format is zero.
4. Execution of BCR 15,0 (that is, an
instruction with a value of 07FO hex) may result in significant
performance degradation. To ensure
optimum performance, the program
should avoid use of BCR 15,0 except
in cases when the serialization or
the checkpoint-synchronization
function is actually required.
5. Note that the relation between the
RR and RX formats in branch-address
specification is not the same as in
operand-address specification. For
branch instructions in the RX
format, the branch address is the
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