Programming Notes
1. An example of the use of the AND
instruction is given in Appendix A.
2. The AND instruction may be used to
set a bit to zero.
3. Accesses to the first operand of
AND (NI) and AND(NC) consist in
fetching a first-operand byte from
storage and subsequently storing
the updated value. These fetch and
store accesses to a particular byte
do not necessarily occur one imme
diately after the other. Thus, the
instructionAND cannot be safely
used to update a location in stor
age if the possibility exists that
anotherCPU or a channel may also
be updating the location. An exam
ple of this effect is shown for OR
(01) in the section "Multiprogram
ming and Multiprocessing Examples"
in Appendix A.BRANCH AND LINK
BALRR, , R:z [RR] , 05' I R t I R:z I 0 8 12 15
BALR"D:z(X:z,B:z) [RX]
'45'I R, I X:z I B:z D:z 0 8 12 16 20 31
Information from the current PSW,
including the updated instruction
address, is loaded as link information
at the first-operand location. Subse
quently, the instruction address is
replaced by the branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
registerR:z are used as the branch
address; however, when theR:z field is
zero, the operation is performed without
branching. The branch address is
computed before general register Rt is
changed.
The link information consists of the
instruction-length code(ILC), the
condition code(CC), the program mask
bits, and the updated instruction
address, arranged in the following
format:
Instruction Address
o 2 48 31
The instruction-length code is 1 or 2.Condition Code: unchanged.
The code remainsProgram Exceptions: None.
Programming Notes
1. An example of the use of theBRANCH AND LINK instruction is given in
Appendix A.
2. When theR, field in the RR format
iszero, the link information is
loaded without branching.
3. WhenBRANCH AND LINK is the target
instruction ofEXECUTE, the
instruction-length code is 2.
4. The format and the contents of the
link information do not depend on
whether thePSW specifies the EC or BC mode. In both modes, the link
information is in the format of the
rightmost 32 bit positions of theBC-mode PSW. BRANCH AND SAVE
BASR R t ,R:z [RR] '00' I R t I R:z I 0 8 12 15
BAS Rt,0,(X
2
,B
2
) [RX]
'4D' Rt X2B, D2 0 8 12 16 20 31
The updated instruction address, with
eight zeros appended on the left, is
saved as link information at the first
operand location. Subsequently, the
instruction address is replaced by the
branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register R2 are used as the branch
address; however, when theR, field is
zero, the operation is performed without
branching. The branch address is
computed before general register Rt is
changed.Chapter 7. General Instructions 7-9
1. An example of the use of the AND
instruction is given in Appendix A.
2. The AND instruction may be used to
set a bit to zero.
3. Accesses to the first operand of
AND (NI) and AND
fetching a first-operand byte from
storage and subsequently storing
the updated value. These fetch and
store accesses to a particular byte
do not necessarily occur one imme
diately after the other. Thus, the
instruction
used to update a location in stor
age if the possibility exists that
another
be updating the location. An exam
ple of this effect is shown for OR
(01) in the section "Multiprogram
ming and Multiprocessing Examples"
in Appendix A.
BALR
BAL
'45'
Information from the current PSW,
including the updated instruction
address, is loaded as link information
at the first-operand location. Subse
quently, the instruction address is
replaced by the branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register
address; however, when the
zero, the operation is performed without
branching. The branch address is
computed before general register Rt is
changed.
The link information consists of the
instruction-length code
condition code
bits, and the updated instruction
address, arranged in the following
format:
Instruction Address
o 2 4
The instruction-length code is 1 or 2.
The code remains
Programming Notes
1. An example of the use of the
Appendix A.
2. When the
is
loaded without branching.
3. When
instruction of
instruction-length code is 2.
4. The format and the contents of the
link information do not depend on
whether the
information is in the format of the
rightmost 32 bit positions of the
BASR R t ,
BAS Rt
2
,B
2
)
'4D' Rt X2
The updated instruction address, with
eight zeros appended on the left, is
saved as link information at the first
operand location. Subsequently, the
instruction address is replaced by the
branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register R2 are used as the branch
address; however, when the
zero, the operation is performed without
branching. The branch address is
computed before general register Rt is
changed.