address specified by X2, B 2 , and
D 2 ; in the RR format, the branch
address is contained in the regis­
ter designated by R2. For
operands, the address specified by X 2 , B 2 , and D2 is the operand address, but the register desig­
nated by R2 contains the operand,
not the operand address.
BRANCH ON COUNT BCTR R t , R2 [RR] '06 ' I R t I R2 I 0 8 12 15
BCT R.,D
2
(X
2
,B
2
) [RX]
, 46 ' I R t I X 2 I B2 D2 0 8 12 16 20 31
A one is subtracted from the first oper­
and, and the result is placed at the
first-operand location. The first oper­ and and result are treated as 32-bit
binary integers, with overflow ignored.
When the result is zero, normal instruc­
tion sequencing proceeds with the updated instruction address. When the
result is not zero, the instruction
address in the current PSW is replaced
by the branch address.
In the RX format, the second-operand
address is used as the branch address.
In the RR format, bits 8-31 of general
register R2 are used as the branch
address; however, when the R:z field is
zero, the operation is performed without
branching. The branch address is computed before general register Rt is changed.
Condition Code: The code remains
unchanged. Program Exceptions: None. Programming Notes
1. An example of the use of the BRANCH ON COUNT instruction is given in
Appendix A.
2. The first operand and result can be
considered as either signed or
unsigned binary integers since the
result of a binary subtraction is
the same in both cases.
3. An initial count of one results in
zero, and no branching takes place;
4.
an initial count of zero results in
-1 and causes branching to be
executed; an initial count of -1
results in -2 and causes branching
to be executed; and so on. In a
loop, branching takes place each time the instruction is executed
until the result is again zero.
Note that, because of the number
range, an initial count of -2
31 results in a positive value of 2
31 - 1.
Counting is performed without
branching when the R2 field in the
RR format contains zero.
BRANCH ON INDEX HIGH
BXH Rt,R3,D2(B2) [RS]
'86' I R t I R3 I B2 D2 0 8 12 16 20 31
BRANCH ON INDEX lOW OR EQUAL BXlE [RS]
o 8 12 16 20 31
An increment is added to the first oper­
and, and the sum is compared with a
compare value. The result of the
comparison determines whether branching
occurs. Subsequently, the sum is placed
at the first-operand location. The
second-operand address is used as a
branch address. The R3 field designates registers containing the increment and
the compare value.
For BRANCH ON INDEX HIGH, when the sum
is high, the instruction address in the
current PSW is replaced by the branch
address. When the sum is low or equal,
normal instruction sequencing proceeds
with the updated instruction address.
For BRANCH ON INDEX lOW OR EQUAL, when
the sum is low or equal, the instruction
address in the current PSW is replaced
by the branch address. When the sum is
high, normal instruction sequencing
proceeds with the updated instruction
address.
When the R3 field is even, it designates
a pair of registers; the contents of the
even and odd registers of the pair are
used as the increment and the compare
value, respectively. When the R3 field
is odd, it designates a single register,
Chapter 7. General Instructions 7-11

the contents of which are used as both
the increment and the compare value.
For purposes of the addition and compar­ all operands and results are
treated as 32-bit signed binary
integers. Overflow caused by the addi­
ti on is ignored.
The original contents of the compare­
value register are used as the compare
value even when that register is also
specified to be the first-operand
location. The branch address is computed before general register Rl is
changed.
The sum is placed at the first-operand
location, regardless of whether the
branch is taken. Condition Code: unchanged.
The code remains
Program Exceptions: None. Programming Notes 1 . Several examples of the use of the BRANCH ON INDEX HIGH and BRANCH ON INDEX LOW OR EQUAL instructions are given in Appendix A.
2. The word "index" in the names of
these instructions indicates that
one of the major purposes is the
incrementing and testing of an
index value. The being
a signed binary integer, may be
used to increase or decrease the
value in general register R\ by an arbitrary amount. COMPARE CR R \ R:z [RR]
'19' I R\ I R2 I 0 8 12 15 C R
1 ,D
2
(X
2
,B
2
) [RX]
'59' I Rl I X 2 I B2 D2 0 8 12 16 20 31
The first operand is compared with the
second and the result is indi­
cated in the condition code. The oper­
ands are treated as 32-bit signed binary
integers.
7-12 System/370 Principles of Operation Resulting Condition Code: o Operands equal
1 First operand low
2 First operand high
3
Program Exceptions:
Access operand 2 of Conly) COMPARE AND SWAP CS [RS]
'BA'
o 8 12 16 20 31 COMPARE DOUBLE AND SWAP CDS [RS]
'BB'
o 8 12 16 20 31
The first and second operands are
compared. If they are equal, the third operand is stored at the second-operand
location. If they are the
second operand is loaded into the
first-operand location. The result of
the comparison is indicated in the
condition code.
For COMPARE AND SWAP, the first and
third operands are 32 bits in with each operand occupying a general
register. The second operand is a word in storage.
For COMPARE DOUBLE AND the first and third operands are 64 bits in
length, with each operand occupying an
even-odd pair of general registers. The
second operand is a doubleword in stor­
age.
When an equal comparison occurs, the third operand is stored at the second­
operand location. The fetch of the
second operand for purposes of compar­
ison and the store into the second­
operand location appear to be a block­
concurrent interlocked-update reference
as observed by other CPUs. When the result of the comparison ;s
unequal, the second-operand location
remains unchanged. However, on some the value may be fetched and
subsequently stored back unchanged at
the second-operand location. This
update appears to be a block-concurrent