interlocked-update reference as observed
by other CPUs. A serialization function is performed
before the operand is fetched and again after the operation is completed.
The second operand of COMPARE AND SWAP must be designated on a word boundary.
The Rt and R3 fields for COMPARE DOUBLE AND SWAP must each designate an even
register, and the second operand for the CDS instruction must be designated on a
doubleword boundary. Otherwise, a spec­
ification exception is recognized.
Resulting Condition Code: o
1
2
3
First and second equal, second operand
by third operand First and second
unequal, first operand by second operand Program Exceptions:
operands replaced operands replaced Access (fetch and store, operand 2)
Operation (if the conditional- swapping facility is not
installed) Specification Programming Notes 1. Several examples of the use of the COMPARE AND SWAP and COMPARE DOUBLE AND SWAP instructions are given in
Appendix A.
2. COMPARE AND SWAP can be used by CPU programs sharing common storage areas in either a multiprogramming or multiprocessing environment.
Two examples are: a. By performing the following
procedure, a CPU program can modify the contents of a stor­ age location even though the
possibility exists that the CPU program may be interrupted by
another CPU program that will update the location or that another CPU program may simul­
taneously update the location. First, the entire word contain­ ing the byte or bytes to be
updated is loaded into a gener­
al register. Next, the updated
value is computed and placed in
another general Then COMPARE AND SWAP is executed
with the Rj field designating
the register that contains the original value and the R3 field
designating the register that contains the updated value. If
the update has been successful, condition code 0 is set. If
the storage location no longer
contains the original value,
the update has not been
successful, the general regis­
ter designated by the R, field of the COMPARE AND SWAP instruction contains the new
current value of the storage
location, and condition code 1 is set. When condition code 1
is set, the CPU program can repeat the procedure using the
new current value.
b. COMPARE AND SWAP can be used
for controlled sharing of a common storage area, including
the capability of leaving a message (in a chained list of
messages) when the common area is in use. To accomplish this,
a word in storage can be used as a control word, with a zero value in the word indicating that the common area is not in
use and that no messages exist,
a negative value indicating that the area is in use and
that no messages exist, and a nonzero positive value indicat­ ing that the common area is in
use and that the value is the address of the most recent message added to the list.
Thus, any number of CPU programs desiring to seize the area can use COMPARE AND SWAP to update the control word to
indicate that the area is 1n
use or to add messages to the
list. The single CPU program
which has seized the area can also safely use COMPARE AND SWAP to remove messages from
the list.
3. COMPARE DOUBLE AND SWAP can be in a manner similar to that
described for COMPARE AND SWAP. In
addition, it has another use. Consider a chained list, with a control word used to address the first message 1n the list, as described in programming note 2b
above. If multiple CPU programs are to b2 permitted to delete
messages by using COMPARE AND SWAP (and not just the single CPU pro­
gram which has seized the common area), there is a possibility the list will be incorrectly updated.
This would occur if, for example, after one CPU program has fetched
the address of the most recent mes­
sage in order to remove the
message, another CPU program
removes the first two messages and
then adds the first message back
into the chain. The first CPU program, on continuing, cannot
easily detect that the list is
changed. By increasing the size of
the control word to a doubleword Chapter 7. General Instructions 7-13

containing both the first message
address and a word with a change
number that is incremented for each modification of the list, and by
using COMPARE DOUBLE AND SWAP to
update both fields together, the
possibility of the list being
incorrectly updated is reduced to a negligible level. That is, an
incorrect update can occur only if
the first CPU program is delayed
while changes exactly equal in
number to a multiple of 2
32 take
place and only if the last change
places the original message address in the control word.
4. COMPARE AND SWAP and COMPARE DOUBLE AND SWAP do not interlock against
storage accesses by channels.
Therefore, the instructions should
not be used to update a location at
which a channel program may store,
since the channel-program data may be lost.
5. For the case of a condition-code
setting of 1, COMPARE AND SWAP and COMPARE DOUBLE AND 5WAP mayor may
not, depending on the model, cause
any of the following to occur for
the second-operand location: a PER storage-alteration event may be
recognized; a protection exception
for storing may be recognized; and, provided no access exception
exists, the change bit may be set
to one. COMPARE HALFWORD CH [RX] , 49'
o 8 12 16 20 31
The first operand is compared with the
second operand, and the result is indi­
cated in the condition code. The second
operand is two bytes in length and is treated as a 16-bit signed binary inte­ ger. The first operand is treated as a
32-bit signed binary integer. Resulting Condition Code: o Operands equal 1 First operand low
2 First operand high
3 Program Exceptions:
Access (fetch, operand 2)
7-14 5ystem/370 Principles of Operation Programming Note
An example of the use HALFWORD instruction is
dix A.
of the COMPARE given in Appen- COMPARE LOGICAL CLR [RR]
'15' I R, I R:z I 0 8 12 15 CL R t ,D:z(X:21 B:z) [RX]
'55' I R, I X:z I B:z D:z o 8 12 16 20 31 CLI [51]
'95' Dl o 8 16 20 31 CLC [55)
'D5' L B:z I I B, I -l.----'-- o 8 16 20 32 36 47
The first operand is compared with the
second operand, and the result is indi­ cated in the condition code.
The comparison proceeds left to right,
byte by byte, and ends as soon as an inequality is found or the end of the
fields is reached. For COMPARE LOGICAL (CL) and COMPARE LOGICAL (CLC), access
exceptions mayor may not be recognized
for the portion of a storage operand to
the right of the first unequal byte.
Resulting Condition Code: o Operands equal
1 First operand low
2 First operand high 3 Program Exceptions:
Access (fetch, operand CLC; fetch, operand CLC) 2, CL and 1, CLI and