EXECUTE [RX]
'44'
o 8 12 16 20 31
The single instruction at the second­
operand address is modified by the
contents of general register R1, and the
resulting instruction, called the target
instruction, is executed.
When the R1 field is not zero, bits 8-15
of the instruction designated by the
second-operand address are ORed with
bits 24-31 of general register R t • The
DRing does not change either the
contents of general register R1 or the
instruction in storage, and it is effec­ tive only for the interpretation of the
instruction to be executed. When the Rt
field is zero, no DRing takes place.
The target instruction may be two, four,
or six bytes in length. The execution
and exception handling of the target instruction are exactly as if the target
instruction were obtained in normal
sequential operation, except for the
instruction address and the
instruction-length code.
The instruction address of the current PSW is increased by the length of
EXECUTE. This updated address and the
instruction-length code of EXECUTE are used, for example, as part of the link
information when the target instruction
is BRANCH AND LINK. When the target
instruction is a successful branching
instruction, the instruction address of
the current PSW is replaced by the
branch address specified by the target
instruction. When the target instruction is in turn
EXECUTE, an execute exception is recog­ nized. The effective address of EXECUTE must be even; otherwise, a specification excep­
tion is recognized. When the target
instruction is two or three halfwords in
length but can be executed without
fetching its second or third halfword,
it is unpredictable whether access
exceptions are recognized for the unused
halfwords. Access exceptions are not
recognized for the second-operand
address when the address is odd.
The second-operand address of EXECUTE is
an instruction address rather than a
logical address; thus, when DAS is
installed and the CPU is in the
secondary-space mode, it is unpredict­
able whether the target instruction is fetched from the primary space or the
secondary space. When DAS ;s not
installed, an instruction address is the
same as a logical address.
Condition Code: The code may be set by
the target instruction. Program Exceptions:
Access (fetch, target instruction)
Execute Specification Programming Notes
1. An example of the
EXECUTE instruction Appendix A.
use of the is given in 2. The DRing of eight bits from the
general register with the desig­
nated instruction permits the indi­
rect specification of the length,
index, mask, immediate-data, regis­
ter, or extended-op-code field.
3. The fetching of the target instruc­
tion is considered to be an
instruction fetch for purposes of
program-event recording and for
purposes of reporting access
exceptions.
4. An access or specification excep­
tion may be caused by EXECUTE or by
the target instruction.
5. When an interruptible instruction
is made the target of EXECUTE, the program normally should not desig­
nate any register updated by the
interruptible instruction as the
R t , X 21 or B2 register for EXECUTE.
Otherwise, on resumption of
execution after an interruption, or
if the instruction is refetched
without an interruption, the
updated values of these registers
will be used in the execution of
EXECUTE. Similarly, the program
should normally not let the desti­
nation field in storage of an interruptible instruction include
the location of EXECUTE, since the new contents of the location may be interpreted when resuming
execution.
6. EXECUTE should be executed in the
secondary-space mode only if the
virtual address of the target
instruction translates to the same
real address by means of both the
primary segment table and secondary
segment table. Otherwise, unpre­
dictable results may occur. Chapter 7. General Instructions 7-19

INSERT CHARACTER IC [RX]
'43'
o 8 12 16 20 31
The byte at the second-operand location
is inserted into bit positions 24-31 of
general register R 1 • The remaining bits
in the register remain unchanged. Condition Code: unchanged. Program Exceptions:
The code
Access (fetch, operand 2) INSERT CHARACTERS UNDER MASK o 8 12 16 20 remains 31
Bytes from contiguous locations begin­
ning at the second-operand address are
inserted into general register Rf under
control of a mask. The contents of the Ml field are used as a mask. These four bits, left to right,
correspond one for one with the four
bytes, left to right, of general regis­ ter R 1 • The byte positions correspon­ ding to ones in the mask are filled,
left to right, with bytes from succes­ sive storage locations beginning at the second-operand address. When the mask
is not zero, the length of the second operand is equal to the number of ones
in the mask. The bytes in the general
register corresponding to zeros in the remain unchanged. The resulting condition code is based on
the mask and on the value of the bits
inserted. When the mask is zero or when
all inserted bits are zeros, the condi­
tion code is set to O. When the
inserted bits are not all zeros, the
code is set according to the leftmost
bit of the storage operand: if this bit
is one, the code is set to 1; if this
bit is zero, the code is set to 2.
When the mask is not zero, exceptions
associated with storage-operand access
are recognized only for the number of
bytes specified by the mask. When the
mask is zero, access exceptions are
recognized for one byte at the second­
operand address. 7-20 System/370 Principles of Operation Resulting Condition Code: 0 All inserted bits zeros, or
mask bits all zeros
1 Leftmost inserted bit one
2 Leftmost inserted bit zero, and
not all inserted bits zeros
3 Program Exceptions:
Access (fetch, operand 2) Programming Notes
1. Examples of the use of the INSERT CHARACTERS UNDER MASK instruction
are given in Appendix A.
2. The condition code for INSERT CHAR­ ACTERS UNDER MASK is defined such
that, when the mask is 1111, the
instruction causes the same condi­
tion code to be set as for LOAD AND TEST. Thus, the instruction may be
used as a storage-to-register
load-and-test operation.
3. INSERT CHARACTERS UNDER MASK with a
mask of 1111 or 0001 performs a
function similar to that of a LOAD (L) or INSERT CHARACTER (IC) instruction, respectively, with the
exception of the condition-code
setting. However, the performance
of INSERT CHARACTERS UNDER MASK may
be sIOL>Jer. LOAD '18' I R, I R:z I o 8 12 15
L R, , D:z (X:z , B :I ) [RX] , 58 ' I R
1 I X 2 I B 2 D 2 o 8 12 16 20 31
The second operand is placed unchanged
at the first-operand location. Condition Code: unchanged. Program Exceptions:
The code remains
Access (fetch, operand 2 of L only)