Programming Notes 1. An example of the use of the PACK instruction is given in Appendix A.
2. PACK may be used to interchange the
two hexadecimal digits in one byte
by specifying a zero in the L, and L2 fields and the same address for
both operands.
3. To remove the zone bits of all
bytes of a field, including the
rightmost byte, both operands must
be extended on the right with a
dummy byte, which subsequently is
ignored in the result field.
4. The storage-operand references for PACK may be multiple-access refer­
ences. (See the secti on "Storage­ Operand Consistency" in Chapter 5, "Program Execution.") SET PROGRAM MASK SPM R, [RR]
o 8 12 15
The first operand is used to set the
condition code and the program mask of
the current PSW. Bits 12-15
ignored.
of the instruction are
Bits 2 and 3 of general register R, replace the condition code, and bits 4-7
replace the program mask. Bits 0, 1,
and 8-31 of general register R, are
ignored.
Condition Code:
specified by bits
register R,. The code is
2 and 3 of Program Exceptions: None. Programming Notes
set as
general
1. Bits 2-7 of the general register
may have been loaded from the PSW by BRANCH AND LINK.
2. SET PROGRAM MASK permits setting of
the condition code and the mask
bits in either the problem state or
the supervisor state.
3. The program should take into
consideration that the setting of
the program mask can have a signif-
icant effect on subsequent
execution of the program. Hot only
do the four mask bits control
whether the corresponding inter­
ruptions occur, but the exponent­
underflow and significance masks
also determine the result which is
obtained.
SHIFT LEFT DOUBLE
o 8 12 16 20 31
The 63-bit numeric part of the signed
first operand is shifted left the number
of bits specified by the second-operand
address, and the result is placed at the
first-operand location.
Bits 12-15
ignored.
of the instruction are
The R, field designates an even-odd pair
of general registers and must designate an even-numbered register; otherwise, a
specification exception is recognized.
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to
be shifted. The remainder of the
address is ignored.
The first operand is treated as a 64-bit
signed binary integer. The sign posi­
tion of the even-numbered register
remains unchanged. The leftmost bit
position of the odd-numbered register
contains a numeric bit, which partic­
ipates in the shift in the same manner as the other numeric bits. Zeros are supplied to the vacated bit positions on
the right.
If one or more bits unlike the sign bit
are shifted out of bit position 1 of the
even-numbered register, an overflow
occurs, and condition code 3 is set. If
the fixed-point-overflow mask bit is
one, a program interruption for fixed­
point overflow occurs.
Resulting Condition Code:
o
1
2
3
Result zero; no overflow
Result less than zero; no over­
flow
Result greater than zero; no
overflow
Overflow Program Exceptions:
Fixed-point overflow
Specification
Chapter 7. General Instructions 7-31
Programming Notes 1. An example of the use of the SHIFT
LEFT DOUBLE instruction is given in Appendix A.
2. The eight shift instructions
provide the following three pairs
of alternatives: left or right,
single or double, and signed or
logical. The signed shifts differ
from the logi cal shi fts in that, in
the signed shifts, overflow is recognized, the condition code is set, and the leftmost bit partic­ ipates as a sign.
3. A zero shift amount in the two
signed double-shift operations
provides a double-length sign and magnitude test.
4. The base register participating in the generation of the second­
operand address permits indirect
specification of the shift amount.
A zero in the B2 field indicates
the absence of indirect shift spec­
ification.
SHIFT LEFT DOUBLE LOGICAL SLDL [RS]
'8D'
o 8 12 16 20 31 The 64-bit first operand is shifted left the number of bits specified by the
second-operand address, and the result
is placed at the first-operand location.
Bits 12-15
ignored.
of the instruction are The R, field designates an even-odd pair
of general registers and must designate
an even-numbered register; otherwise, a
specification exception is recognized.
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to be shifted. The remainder of the
address is ignored. All 64 bits of the first operand partic­ ipate in the shift. Bits shifted out of
bit position 0 of the even-numbered
register are not inspected and are lost.
Zeros are supplied to the vacated bit
positions on the right.
Condition Code: unchanged. The code remains 7-32 System/370 Principles of Operation Program Exceptions:
Specification
SHIFT LEFT SINGLE
SLA [RS]
'8B'
o 8 12 16 20 31
The 31-bit numeric part of the signed
first operand is shifted left the number
of bits specified by the second-operand
address, and the result is placed at the
first-operand location.
Bits 12-15
ignored.
of the instruction are
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to
be shifted. The remainder of the
address is ignored. The first operand is treated as a 32-bit
signed binary integer. The sign of the
first operand remains unchanged. All 31
numeric bits of the operand participate
in the left shift. Zeros are supplied
to the vacated bit positions on the
right.
If one or more bits unlike the sign bit
are shifted out of bit position 1, an
overflow occurs, and condition code 3 is
set. If the fixed-poi nt-overflow mask
bit is one, a program interruption for
fixed-point overflow occurs.
Resulting Condition Code:
o
1
2
3
Result zero; no overflow Result less than zero; no over­
flow
Result greater than zero; no
overflow Overflow Program Exceptions:
Fixed-point overflow Programming Notes
1. An example of the use of the SHIFT
LEFT SINGLE instruction is given in
Appendix A.
2. For numbers with a value greater
than or equal to -2
30
and less than
2
30
, a left shift of one bit posi­
tion is equivalent to multiplying
the number by 2.
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